.include
Search Path: -I path
.abort
.ABORT
(COFF)
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abs-expr,
abs-expr,
abs-expr
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This file is a user guide to the gnu assembler as (GNU Binutils) version 2.30.52.
This document is distributed under the terms of the GNU Free Documentation License. A copy of the license is included in the section entitled “GNU Free Documentation License”.
Here is a brief summary of how to invoke as. For details, see Command-Line Options.
as [-a[cdghlns][=file]] [--alternate] [-D] [--compress-debug-sections] [--nocompress-debug-sections] [--debug-prefix-map old=new] [--defsym sym=val] [-f] [-g] [--gstabs] [--gstabs+] [--gdwarf-2] [--gdwarf-sections] [--help] [-I dir] [-J] [-K] [-L] [--listing-lhs-width=NUM] [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM] [--listing-cont-lines=NUM] [--keep-locals] [--no-pad-sections] [-o objfile] [-R] [--hash-size=NUM] [--reduce-memory-overheads] [--statistics] [-v] [-version] [--version] [-W] [--warn] [--fatal-warnings] [-w] [-x] [-Z] [@FILE] [--sectname-subst] [--size-check=[error|warning]] [--elf-stt-common=[no|yes]] [--generate-missing-build-notes=[no|yes]] [--target-help] [target-options] [--|files ...] Target Alpha options: [-mcpu] [-mdebug | -no-mdebug] [-replace | -noreplace] [-relax] [-g] [-Gsize] [-F] [-32addr] Target ARC options: [-mcpu=cpu] [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS] [-mcode-density] [-mrelax] [-EB|-EL] Target ARM options: [-mcpu=processor[+extension...]] [-march=architecture[+extension...]] [-mfpu=floating-point-format] [-mfloat-abi=abi] [-meabi=ver] [-mthumb] [-EB|-EL] [-mapcs-32|-mapcs-26|-mapcs-float| -mapcs-reentrant] [-mthumb-interwork] [-k] Target Blackfin options: [-mcpu=processor[-sirevision]] [-mfdpic] [-mno-fdpic] [-mnopic] Target CRIS options: [--underscore | --no-underscore] [--pic] [-N] [--emulation=criself | --emulation=crisaout] [--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32] Target D10V options: [-O] Target D30V options: [-O|-n|-N] Target EPIPHANY options: [-mepiphany|-mepiphany16] Target H8/300 options: [-h-tick-hex] Target i386 options: [--32|--x32|--64] [-n] [-march=CPU[+EXTENSION...]] [-mtune=CPU] Target IA-64 options: [-mconstant-gp|-mauto-pic] [-milp32|-milp64|-mlp64|-mp64] [-mle|mbe] [-mtune=itanium1|-mtune=itanium2] [-munwind-check=warning|-munwind-check=error] [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] [-x|-xexplicit] [-xauto] [-xdebug] Target IP2K options: [-mip2022|-mip2022ext] Target M32C options: [-m32c|-m16c] [-relax] [-h-tick-hex] Target M32R options: [--m32rx|--[no-]warn-explicit-parallel-conflicts| --W[n]p] Target M680X0 options: [-l] [-m68000|-m68010|-m68020|...] Target M68HC11 options: [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg] [-mshort|-mlong] [-mshort-double|-mlong-double] [--force-long-branches] [--short-branches] [--strict-direct-mode] [--print-insn-syntax] [--print-opcodes] [--generate-example] Target MCORE options: [-jsri2bsr] [-sifilter] [-relax] [-mcpu=[210|340]] Target MICROBLAZE options: Target MIPS options: [-nocpp] [-EL] [-EB] [-O[optimization level]] [-g[debug level]] [-G num] [-KPIC] [-call_shared] [-non_shared] [-xgot [-mvxworks-pic] [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] [-mfp64] [-mgp64] [-mfpxx] [-modd-spreg] [-mno-odd-spreg] [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2] [-mips64r3] [-mips64r5] [-mips64r6] [-construct-floats] [-no-construct-floats] [-mignore-branch-isa] [-mno-ignore-branch-isa] [-mnan=encoding] [-trap] [-no-break] [-break] [-no-trap] [-mips16] [-no-mips16] [-mmips16e2] [-mno-mips16e2] [-mmicromips] [-mno-micromips] [-msmartmips] [-mno-smartmips] [-mips3d] [-no-mips3d] [-mdmx] [-no-mdmx] [-mdsp] [-mno-dsp] [-mdspr2] [-mno-dspr2] [-mdspr3] [-mno-dspr3] [-mmsa] [-mno-msa] [-mxpa] [-mno-xpa] [-mmt] [-mno-mt] [-mmcu] [-mno-mcu] [-mcrc] [-mno-crc] [-mginv] [-mno-ginv] [-mloongson-mmi] [-mno-loongson-mmi] [-mloongson-cam] [-mno-loongson-cam] [-mloongson-ext] [-mno-loongson-ext] [-mloongson-ext2] [-mno-loongson-ext2] [-minsn32] [-mno-insn32] [-mfix7000] [-mno-fix7000] [-mfix-rm7000] [-mno-fix-rm7000] [-mfix-vr4120] [-mno-fix-vr4120] [-mfix-vr4130] [-mno-fix-vr4130] [-mfix-r5900] [-mno-fix-r5900] [-mdebug] [-no-mdebug] [-mpdr] [-mno-pdr] Target MMIX options: [--fixed-special-register-names] [--globalize-symbols] [--gnu-syntax] [--relax] [--no-predefined-symbols] [--no-expand] [--no-merge-gregs] [-x] [--linker-allocated-gregs] Target PDP11 options: [-mpic|-mno-pic] [-mall] [-mno-extensions] [-mextension|-mno-extension] [-mcpu] [-mmachine] Target picoJava options: [-mb|-me] Target PowerPC options: [-a32|-a64] [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko| -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500| -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x| -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2| -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom] [-many] [-maltivec|-mvsx|-mhtm|-mvle] [-mregnames|-mno-regnames] [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] [-msolaris|-mno-solaris] [-nops=count] Target RL78 options: [-mg10] [-m32bit-doubles|-m64bit-doubles] Target RX options: [-mlittle-endian|-mbig-endian] [-m32bit-doubles|-m64bit-doubles] [-muse-conventional-section-names] [-msmall-data-limit] [-mpid] [-mrelax] [-mint-register=number] [-mgcc-abi|-mrx-abi] Target s390 options: [-m31|-m64] [-mesa|-mzarch] [-march=CPU] [-mregnames|-mno-regnames] [-mwarn-areg-zero] Target SCORE options: [-EB][-EL][-FIXDD][-NWARN] [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] [-march=score7][-march=score3] [-USE_R1][-KPIC][-O0][-G num][-V] Target SPARC options: [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3 -Asparcvisr|-Asparc5] [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5 -bump] [-32|-64] [--enforce-aligned-data][--dcti-couples-detect] Target TIC54X options: [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] [-merrors-to-file <filename>|-me <filename>] Target TIC6X options: [-march=arch] [-mbig-endian|-mlittle-endian] [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far] [-mpic|-mno-pic] Target TILE-Gx options: [-m32|-m64][-EB][-EL] Target Xtensa options: [--[no-]text-section-literals] [--[no-]auto-litpools] [--[no-]absolute-literals] [--[no-]target-align] [--[no-]longcalls] [--[no-]transform] [--rename-section oldname=newname] [--[no-]trampolines] Target Z80 options: [-z80] [-r800] [ -ignore-undocumented-instructions] [-Wnud] [ -ignore-unportable-instructions] [-Wnup] [ -warn-undocumented-instructions] [-Wud] [ -warn-unportable-instructions] [-Wup] [ -forbid-undocumented-instructions] [-Fud] [ -forbid-unportable-instructions] [-Fup]
@
fileOptions in file are separated by whitespace. A whitespace
character may be included in an option by surrounding the entire
option in either single or double quotes. Any character (including a
backslash) may be included by prefixing the character to be included
with a backslash. The file may itself contain additional
@file options; any such options will be processed recursively.
-a[cdghlmns]
-ac
-ad
-ag
-ah
-al
-am
-an
-as
=file
You may combine these options; for example, use ‘-aln’ for assembly
listing without forms processing. The ‘=file’ option, if used, must be
the last one. By itself, ‘-a’ defaults to ‘-ahls’.
--alternate
.altmacro
.
--compress-debug-sections
--compress-debug-sections=none
--compress-debug-sections=zlib
--compress-debug-sections=zlib-gnu
--compress-debug-sections=zlib-gabi
--nocompress-debug-sections
-D
--debug-prefix-map
old=
new--defsym
sym=
value.set
pseudo-op.
-f
-g
--gen-debug
--gstabs
--gstabs+
--gdwarf-2
--gdwarf-sections
--size-check=error
--size-check=warning
--elf-stt-common=no
--elf-stt-common=yes
STT_COMMON
type. The default can be controlled
by a configure option --enable-elf-stt-common.
--generate-missing-build-notes=yes
--generate-missing-build-notes=no
--help
--target-help
-I
dir.include
directives.
-J
-K
-L
--keep-locals
--listing-lhs-width=
number--listing-lhs-width2=
number--listing-rhs-width=
number--listing-cont-lines=
number--no-pad-sections
-o
objfile-R
--hash-size=
number--reduce-memory-overheads
--sectname-subst
.section
name.
--statistics
--strip-local-absolute
-v
-version
--version
-W
--no-warn
--fatal-warnings
--warn
-w
-x
-Z
-- |
files ...
See Alpha Options, for the options available when as is configured for an Alpha processor.
The following options are available when as is configured for an ARC processor.
-mcpu=
cpu-EB | -EL
-mcode-density
The following options are available when as is configured for the ARM processor family.
-mcpu=
processor[+
extension...]
-march=
architecture[+
extension...]
-mfpu=
floating-point-format-mfloat-abi=
abi-mthumb
-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
-EB | -EL
-mthumb-interwork
-mccs
-k
See Blackfin Options, for the options available when as is configured for the Blackfin processor family.
See the info pages for documentation of the CRIS-specific options.
The following options are available when as is configured for a D10V processor.
-O
The following options are available when as is configured for a D30V processor.
-O
-n
-N
The following options are available when as is configured for the Adapteva EPIPHANY series.
See Epiphany Options, for the options available when as is configured for an Epiphany processor.
See i386-Options, for the options available when as is configured for an i386 processor.
The following options are available when as is configured for the Ubicom IP2K series.
-mip2022ext
-mip2022
The following options are available when as is configured for the Renesas M32C and M16C processors.
-m32c
-m16c
-relax
-h-tick-hex
The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series.
--m32rx
--warn-explicit-parallel-conflicts or --Wp
--no-warn-explicit-parallel-conflicts or --Wnp
The following options are available when as is configured for the Motorola 68000 series.
-l
-m68000 | -m68008 | -m68010 | -m68020 | -m68030
| -m68040 | -m68060 | -m68302 | -m68331 | -m68332
| -m68333 | -m68340 | -mcpu32 | -m5200
-m68881 | -m68882 | -mno-68881 | -mno-68882
-m68851 | -mno-68851
For details about the PDP-11 machine dependent features options, see PDP-11-Options.
-mpic | -mno-pic
-mall
-mall-extensions
-mno-extensions
-m
extension | -mno-
extension-m
cpu-m
machineThe following options are available when as is configured for a picoJava processor.
The following options are available when as is configured for the Motorola 68HC11 or 68HC12 series.
-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg
--xgate-ramoffset
-mshort
-mlong
-mshort-double
-mlong-double
--force-long-branches
-S | --short-branches
--strict-direct-mode
--print-insn-syntax
--print-opcodes
--generate-example
The following options are available when as is configured for the SPARC architecture:
-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
-Av8plus | -Av8plusa | -Av9 | -Av9a
‘-Av8plus’ and ‘-Av8plusa’ select a 32 bit environment. ‘-Av9’ and ‘-Av9a’ select a 64 bit environment.
‘-Av8plusa’ and ‘-Av9a’ enable the SPARC V9 instruction set with
UltraSPARC extensions.
-xarch=v8plus | -xarch=v8plusa
-bump
The following options are available when as is configured for the 'c54x architecture.
-mfar-mode
-mcpu=
CPU_VERSION-merrors-to-file
FILENAMEThe following options are available when as is configured for a MIPS processor.
-G
numgp
register. It is only accepted for targets that
use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
-EB
-EL
-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips32r3
-mips32r5
-mips32r6
-mips64
-mips64r2
-mips64r3
-mips64r5
-mips64r6
-march=
cpu-mtune=
cpu-mfix7000
-mno-fix7000
-mfix-rm7000
-mno-fix-rm7000
-mfix-r5900
-mno-fix-r5900
nop
instruction there
instead. The short loop bug under certain conditions causes loops to
execute only once or twice, due to a hardware bug in the R5900 chip.
-mdebug
-no-mdebug
-mpdr
-mno-pdr
.pdr
sections.
-mgp32
-mfp32
-mgp64
-mfp64
-mfpxx
-modd-spreg
-mno-odd-spreg
-mips16
-no-mips16
.module mips16
at the start of the assembly file. ‘-no-mips16’
turns off this option.
-mmips16e2
-mno-mips16e2
.module mips16e2
at the start of the assembly file.
‘-mno-mips16e2’ turns off this option.
-mmicromips
-mno-micromips
.module micromips
at the start of the assembly file.
‘-mno-micromips’ turns off this option. This is equivalent to putting
.module nomicromips
at the start of the assembly file.
-msmartmips
-mno-smartmips
.module smartmips
at the start of the assembly
file. ‘-mno-smartmips’ turns off this option.
-mips3d
-no-mips3d
-mdmx
-no-mdmx
-mdsp
-mno-dsp
-mdspr2
-mno-dspr2
-mdspr3
-mno-dspr3
-mmsa
-mno-msa
-mxpa
-mno-xpa
-mmt
-mno-mt
-mmcu
-mno-mcu
-mcrc
-mno-crc
-mginv
-mno-ginv
-mloongson-mmi
-mno-loongson-mmi
-mloongson-cam
-mno-loongson-cam
-mloongson-ext
-mno-loongson-ext
-mloongson-ext2
-mno-loongson-ext2
-minsn32
-mno-insn32
.set insn32
at
the start of the assembly file. ‘-mno-insn32’ turns off this
option. This is equivalent to putting .set noinsn32
at the
start of the assembly file. By default ‘-mno-insn32’ is
selected, allowing all instructions to be used.
--construct-floats
--no-construct-floats
--relax-branch
--no-relax-branch
-mignore-branch-isa
-mno-ignore-branch-isa
-mnan=
encoding--emulation=
nameThe available configuration names are: ‘mipself’, ‘mipslelf’ and
‘mipsbelf’. Choosing ‘mipself’ now has no effect, since the output
is always ELF. ‘mipslelf’ and ‘mipsbelf’ select little- and
big-endian output respectively, but ‘-EL’ and ‘-EB’ are now the
preferred options instead.
-nocpp
--trap
--no-trap
--break
--no-break
-n
The following options are available when as is configured for an MCore processor.
-jsri2bsr
-nojsri2bsr
-sifilter
-nosifilter
-relax
-mcpu=[210|340]
-EB
-EL
See the info pages for documentation of the MMIX-specific options.
See PowerPC-Opts, for the options available when as is configured for a PowerPC processor.
See the info pages for documentation of the RX-specific options.
The following options are available when as is configured for the s390 processor family.
-m31
-m64
-mesa
-mzarch
-march=
processor-mregnames
-mno-regnames
-mwarn-areg-zero
See TIC6X Options, for the options available when as is configured for a TMS320C6000 processor.
See TILE-Gx Options, for the options available when as is configured for a TILE-Gx processor.
See Xtensa Options, for the options available when as is configured for an Xtensa processor.
The following options are available when as is configured for a Z80 family processor.
-z80
-r800
-ignore-undocumented-instructions
-Wnud
-ignore-unportable-instructions
-Wnup
-warn-undocumented-instructions
-Wud
-warn-unportable-instructions
-Wup
-forbid-undocumented-instructions
-Fud
-forbid-unportable-instructions
-Fup
This manual is intended to describe what you need to know to use gnu as. We cover the syntax expected in source files, including notation for symbols, constants, and expressions; the directives that as understands; and of course how to invoke as.
This manual also describes some of the machine-dependent features of various flavors of the assembler.
On the other hand, this manual is not intended as an introduction to programming in assembly language—let alone programming in general! In a similar vein, we make no attempt to introduce the machine architecture; we do not describe the instruction set, standard mnemonics, registers or addressing modes that are standard to a particular architecture. You may want to consult the manufacturer's machine architecture manual for this information.
gnu as is really a family of assemblers. If you use (or have used) the gnu assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called pseudo-ops) and assembler syntax.
as is primarily intended to assemble the output of the
gnu C compiler gcc
for use by the linker
ld
. Nevertheless, we've tried to make as
assemble correctly everything that other assemblers for the same
machine would assemble.
Any exceptions are documented explicitly (see Machine Dependencies).
This doesn't mean as always uses the same syntax as another
assembler for the same architecture; for example, we know of several
incompatible versions of 680x0 assembly language syntax.
Unlike older assemblers, as is designed to assemble a source
program in one pass of the source file. This has a subtle impact on the
.org directive (see .org
).
The gnu assembler can be configured to produce several alternative object file formats. For the most part, this does not affect how you write assembly language programs; but directives for debugging symbols are typically different in different file formats. See Symbol Attributes.
After the program name as, the command line may contain options and file names. Options may appear in any order, and may be before, after, or between file names. The order of file names is significant.
-- (two hyphens) by itself names the standard input file explicitly, as one of the files for as to assemble.
Except for ‘--’ any command-line argument that begins with a hyphen (‘-’) is an option. Each option changes the behavior of as. No option changes the way another option works. An option is a ‘-’ followed by one or more letters; the case of the letter is important. All options are optional.
Some options expect exactly one file name to follow them. The file name may either immediately follow the option's letter (compatible with older assemblers) or it may be the next command argument (gnu standard). These two command lines are equivalent:
as -o my-object-file.o mumble.s as -omy-object-file.o mumble.s
We use the phrase source program, abbreviated source, to describe the program input to one run of as. The program may be in one or more files; how the source is partitioned into files doesn't change the meaning of the source.
The source program is a concatenation of the text in all the files, in the order specified.
Each time you run as it assembles exactly one source program. The source program is made up of one or more files. (The standard input is also a file.)
You give as a command line that has zero or more input file names. The input files are read (from left file name to right). A command-line argument (in any position) that has no special meaning is taken to be an input file name.
If you give as no file names it attempts to read one input file from the as standard input, which is normally your terminal. You may have to type <ctl-D> to tell as there is no more program to assemble.
Use ‘--’ if you need to explicitly name the standard input file in your command line.
If the source is empty, as produces a small, empty object file.
There are two ways of locating a line in the input file (or files) and either may be used in reporting error messages. One way refers to a line number in a physical file; the other refers to a line number in a “logical” file. See Error and Warning Messages.
Physical files are those files named in the command line given to as.
Logical files are simply names declared explicitly by assembler
directives; they bear no relation to physical files. Logical file names help
error messages reflect the original source file, when as source
is itself synthesized from other files. as understands the
‘#’ directives emitted by the gcc
preprocessor. See also
.file
.
Every time you run as it produces an output file, which is
your assembly language program translated into numbers. This file
is the object file. Its default name is a.out
.
You can give it another name by using the -o option. Conventionally,
object file names end with .o. The default name is used for historical
reasons: older assemblers were capable of assembling self-contained programs
directly into a runnable program. (For some formats, this isn't currently
possible, but it can be done for the a.out
format.)
The object file is meant for input to the linker ld
. It contains
assembled program code, information to help ld
integrate
the assembled program into a runnable file, and (optionally) symbolic
information for the debugger.
as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly.
Warning messages have the format
file_name:NNN:Warning Message Text
(where NNN is a line number). If both a logical file name
(see .file
) and a logical line number
(see .line
)
have been given then they will be used, otherwise the file name and line number
in the current assembler source file will be used. The message text is
intended to be self explanatory (in the grand Unix tradition).
Note the file name must be set via the logical version of the .file
directive, not the DWARF2 version of the .file
directive. For example:
.file 2 "bar.c" error_assembler_source .file "foo.c" .line 30 error_c_source
produces this output:
Assembler messages: asm.s:2: Error: no such instruction: `error_assembler_source' foo.c:31: Error: no such instruction: `error_c_source'
Error messages have the format
file_name:NNN:FATAL:Error Message Text
The file name and line number are derived as for warning messages. The actual message text may be rather less explanatory because many of them aren't supposed to happen.
This chapter describes command-line options available in all versions of the gnu assembler; see Machine Dependencies, for options specific to particular machine architectures.
If you are invoking as via the gnu C compiler, you can use the ‘-Wa’ option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the ‘-Wa’) by commas. For example:
gcc -c -g -O -Wa,-alh,-L file.c
This passes two options to the assembler: ‘-alh’ (emit a listing to standard output with high-level and assembly source) and ‘-L’ (retain local symbols in the symbol table).
Usually you do not need to use this ‘-Wa’ mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the gnu compiler driver with the ‘-v’ option to see precisely what options it passes to each compilation pass, including the assembler.)
These options enable listing output from the assembler. By itself, ‘-a’ requests high-level, assembly, and symbols listing. You can use other letters to select specific options for the list: ‘-ah’ requests a high-level language listing, ‘-al’ requests an output-program assembly listing, and ‘-as’ requests a symbol table listing. High-level listings require that a compiler debugging option like ‘-g’ be used, and that assembly listings (‘-al’) be requested also.
Use the ‘-ag’ option to print a first section with general assembly information, like as version, switches passed, or time stamp.
Use the ‘-ac’ option to omit false conditionals from a listing. Any lines
which are not assembled because of a false .if
(or .ifdef
, or any
other conditional), or a true .if
followed by an .else
, will be
omitted from the listing.
Use the ‘-ad’ option to omit debugging directives from the listing.
Once you have specified one of these options, you can further control
listing output and its appearance using the directives .list
,
.nolist
, .psize
, .eject
, .title
, and
.sbttl
.
The ‘-an’ option turns off all forms processing.
If you do not request listing output with one of the ‘-a’ options, the
listing-control directives have no effect.
The letters after ‘-a’ may be combined into one option, e.g., ‘-aln’.
Note if the assembler source is coming from the standard input (e.g.,
because it
is being created by gcc
and the ‘-pipe’ command-line switch
is being used) then the listing will not contain any comments or preprocessor
directives. This is because the listing code buffers input source lines from
stdin only after they have been preprocessed by the assembler. This reduces
memory usage and makes the code more efficient.
Begin in alternate macro mode, see .altmacro
.
This option has no effect whatsoever, but it is accepted to make it more likely that scripts written for other assemblers also work with as.
‘-f’ should only be used when assembling programs written by a (trusted) compiler. ‘-f’ stops the assembler from doing whitespace and comment preprocessing on the input file(s) before assembling them. See Preprocessing.
Warning: if you use ‘-f’ when the files actually need to be preprocessed (if they contain comments, for example), as does not work correctly.
.include
Search Path: -I pathUse this option to add a path to the list of directories
as searches for files specified in .include
directives (see .include
). You may use -I as
many times as necessary to include a variety of paths. The current
working directory is always searched first; after that, as
searches any ‘-I’ directories in the same order as they were
specified (left to right) on the command line.
as sometimes alters the code emitted for directives of the
form ‘.word sym1-sym2’. See .word
.
You can use the ‘-K’ option if you want a warning issued when this
is done.
Symbols beginning with system-specific local label prefixes, typically
‘.L’ for ELF systems or ‘L’ for traditional a.out systems, are
called local symbols. See Symbol Names. Normally you do not see
such symbols when debugging, because they are intended for the use of
programs (like compilers) that compose assembler programs, not for your
notice. Normally both as and ld
discard
such symbols, so you do not normally debug with them.
This option tells as to retain those local symbols
in the object file. Usually if you do this you also tell the linker
ld
to preserve those symbols.
The listing feature of the assembler can be enabled via the command-line switch
‘-a’ (see a). This feature combines the input source file(s) with a
hex dump of the corresponding locations in the output object file, and displays
them as a listing file. The format of this listing can be controlled by
directives inside the assembler source (i.e., .list
(see List),
.title
(see Title), .sbttl
(see Sbttl),
.psize
(see Psize), and
.eject
(see Eject) and also by the following switches:
--listing-lhs-width=‘
number’
--listing-lhs-width2=‘
number’
--listing-rhs-width=‘
number’
--listing-cont-lines=‘
number’
The -M or --mri option selects MRI compatibility mode. This
changes the syntax and pseudo-op handling of as to make it
compatible with the ASM68K
assembler from Microtec Research.
The exact nature of the
MRI syntax will not be documented here; see the MRI manuals for more
information. Note in particular that the handling of macros and macro
arguments is somewhat different. The purpose of this option is to permit
assembling existing MRI assembler code using as.
The MRI compatibility is not complete. Certain operations of the MRI assembler depend upon its object file format, and can not be supported using other object file formats. Supporting these would require enhancing each object file format individually. These are:
The m68k MRI assembler supports common sections which are merged by the linker. Other object file formats do not support this. as handles common sections by treating them as a single common symbol. It permits local symbols to be defined within a common section, but it can not support global symbols, since it has no way to describe them.
The MRI assemblers support relocations against a negated section address, and relocations which combine the start addresses of two or more sections. These are not support by other object file formats.
END
pseudo-op specifying start address
The MRI END
pseudo-op permits the specification of a start address.
This is not supported by other object file formats. The start address may
instead be specified using the -e option to the linker, or in a linker
script.
IDNT
, .ident
and NAME
pseudo-ops
The MRI IDNT
, .ident
and NAME
pseudo-ops assign a module
name to the output file. This is not supported by other object file formats.
ORG
pseudo-op
The m68k MRI ORG
pseudo-op begins an absolute section at a given
address. This differs from the usual as .org
pseudo-op,
which changes the location within the current section. Absolute sections are
not supported by other object file formats. The address of a section may be
assigned within a linker script.
There are some other features of the MRI assembler which are not supported by as, typically either because they are difficult or because they seem of little consequence. Some of these may be supported in future releases.
EBCDIC strings are not supported.
Packed binary coded decimal is not supported. This means that the DC.P
and DCB.P
pseudo-ops are not supported.
FEQU
pseudo-op
The m68k FEQU
pseudo-op is not supported.
NOOBJ
pseudo-op
The m68k NOOBJ
pseudo-op is not supported.
OPT
branch control options
The m68k OPT
branch control options—B
, BRS
, BRB
,
BRL
, and BRW
—are ignored. as automatically
relaxes all branches, whether forward or backward, to an appropriate size, so
these options serve no purpose.
OPT
list control options
The following m68k OPT
list control options are ignored: C
,
CEX
, CL
, CRE
, E
, G
, I
, M
,
MEX
, MC
, MD
, X
.
OPT
options
The following m68k OPT
options are ignored: NEST
, O
,
OLD
, OP
, P
, PCO
, PCR
, PCS
, R
.
OPT
D
option is default
The m68k OPT
D
option is the default, unlike the MRI assembler.
OPT NOD
may be used to turn it off.
XREF
pseudo-op.
The m68k XREF
pseudo-op is ignored.
as can generate a dependency file for the file it creates. This
file consists of a single rule suitable for make
describing the
dependencies of the main source file.
The rule is written to the file named in its argument.
This feature is used in the automatic updating of makefiles.
Normally the assembler will pad the end of each output section up to its alignment boundary. But this can waste space, which can be significant on memory constrained targets. So the --no-pad-sections option will disable this behaviour.
There is always one object file output when you run as. By default it has the name a.out. You use this option (which takes exactly one filename) to give the object file a different name.
Whatever the object file is called, as overwrites any existing file of the same name.
-R tells as to write the object file as if all data-section data lives in the text section. This is only done at the very last moment: your binary data are the same, but data section parts are relocated differently. The data section part of your object file is zero bytes long because all its bytes are appended to the text section. (See Sections and Relocation.)
When you specify -R it would be possible to generate shorter address displacements (because we do not have to cross between text and data section). We refrain from doing this simply for compatibility with older versions of as. In future, -R may work this way.
When as is configured for COFF or ELF output, this option is only useful if you use sections named ‘.text’ and ‘.data’.
-R is not supported for any of the HPPA targets. Using -R generates a warning from as.
Use ‘--statistics’ to display two statistics about the resources used by as: the maximum amount of space allocated during the assembly (in bytes), and the total execution time taken for the assembly (in cpu seconds).
For some targets, the output of as is different in some ways from the output of some existing assembler. This switch requests as to use the traditional format instead.
For example, it disables the exception frame optimizations which
as normally does by default on gcc
output.
You can find out what version of as is running by including the option ‘-v’ (which you can also spell as ‘-version’) on the command line.
as should never give a warning or error message when assembling compiler output. But programs written by people often cause as to give a warning that a particular assumption was made. All such warnings are directed to the standard error file.
If you use the -W and --no-warn options, no warnings are issued. This only affects the warning messages: it does not change any particular of how as assembles your file. Errors, which stop the assembly, are still reported.
If you use the --fatal-warnings option, as considers files that generate warnings to be in error.
You can switch these options off again by specifying --warn, which causes warnings to be output as usual.
After an error message, as normally produces no output. If for some reason you are interested in object file output even after as gives an error message on your program, use the ‘-Z’ option. If there are any errors, as continues anyways, and writes an object file after a final warning message of the form ‘n errors, m warnings, generating bad object file.’
This chapter describes the machine-independent syntax allowed in a source file. as syntax is similar to what many other assemblers use; it is inspired by the BSD 4.2 assembler, except that as does not assemble Vax bit-fields.
It does not do macro processing, include file handling, or
anything else you may get from your C compiler's preprocessor. You can
do include file processing with the .include
directive
(see .include
). You can use the gnu C compiler driver
to get other “CPP” style preprocessing by giving the input file a
‘.S’ suffix. See Options Controlling the Kind of Output.
Excess whitespace, comments, and character constants cannot be used in the portions of the input text that are not preprocessed.
If the first line of an input file is #NO_APP
or if you use the
‘-f’ option, whitespace and comments are not removed from the input file.
Within an input file, you can ask for whitespace and comment removal in
specific portions of the by putting a line that says #APP
before the
text that may contain whitespace or comments, and putting a line that says
#NO_APP
after this text. This feature is mainly intend to support
asm
statements in compilers whose output is otherwise free of comments
and whitespace.
Whitespace is one or more blanks or tabs, in any order. Whitespace is used to separate symbols, and to make programs neater for people to read. Unless within character constants (see Character Constants), any whitespace means the same as exactly one space.
There are two ways of rendering comments to as. In both cases the comment is equivalent to one space.
Anything from ‘/*’ through the next ‘*/’ is a comment. This means you may not nest these comments.
/* The only way to include a newline ('\n') in a comment is to use this sort of comment. */ /* This sort of comment does not nest. */
Anything from a line comment character up to the next newline is considered a comment and is ignored. The line comment character is target specific, and some targets multiple comment characters. Some targets also have line comment characters that only work if they are the first character on a line. Some targets use a sequence of two characters to introduce a line comment. Some targets can also change their line comment characters depending upon command-line options that have been used. For more details see the Syntax section in the documentation for individual targets.
If the line comment character is the hash sign (‘#’) then it still has the special ability to enable and disable preprocessing (see Preprocessing) and to specify logical line numbers:
To be compatible with past assemblers, lines that begin with ‘#’ have a special interpretation. Following the ‘#’ should be an absolute expression (see Expressions): the logical line number of the next line. Then a string (see Strings) is allowed: if present it is a new logical file name. The rest of the line, if any, should be whitespace.
If the first non-whitespace characters on the line are not numeric, the line is ignored. (Just like a comment.)
# This is an ordinary comment. # 42-6 "new_file_name" # New logical file name # This is logical line # 36.
This feature is deprecated, and may disappear from future versions of as.
A symbol is one or more characters chosen from the set of all
letters (both upper and lower case), digits and the three characters
‘_.$’.
On most machines, you can also use $
in symbol names; exceptions
are noted in Machine Dependencies.
No symbol may begin with a digit. Case is significant.
There is no length limit; all characters are significant. Multibyte characters
are supported. Symbols are delimited by characters not in that set, or by the
beginning of a file (since the source program must end with a newline, the end
of a file is not a possible symbol delimiter). See Symbols.
Symbol names may also be enclosed in double quote "
characters. In such
cases any characters are allowed, except for the NUL character. If a double
quote character is to be included in the symbol name it must be preceeded by a
backslash \
character.
A statement ends at a newline character (‘\n’) or a line separator character. The line separator character is target specific and described in the Syntax section of each target's documentation. Not all targets support a line separator character. The newline or line separator character is considered to be part of the preceding statement. Newlines and separators within character constants are an exception: they do not end statements.
It is an error to end any statement with end-of-file: the last character of any input file should be a newline.
An empty statement is allowed, and may include whitespace. It is ignored.
A statement begins with zero or more labels, optionally followed by a key symbol which determines what kind of statement it is. The key symbol determines the syntax of the rest of the statement. If the symbol begins with a dot ‘.’ then the statement is an assembler directive: typically valid for any computer. If the symbol begins with a letter the statement is an assembly language instruction: it assembles into a machine language instruction. Different versions of as for different computers recognize different instructions. In fact, the same symbol may represent a different instruction in a different computer's assembly language.
A label is a symbol immediately followed by a colon (:
).
Whitespace before a label or after a colon is permitted, but you may not
have whitespace between a label's symbol and its colon. See Labels.
For HPPA targets, labels need not be immediately followed by a colon, but the definition of a label must begin in column zero. This also implies that only one label may be defined on each line.
label: .directive followed by something another_label: # This is an empty statement. instruction operand_1, operand_2, ...
A constant is a number, written so that its value is known by inspection, without knowing any context. Like this:
.byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. .ascii "Ring the bell\7" # A string constant. .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. .float 0f-314159265358979323846264338327\ 95028841971.693993751E-40 # - pi, a flonum.
There are two kinds of character constants. A character stands for one character in one byte and its value may be used in numeric expressions. String constants (properly called string literals) are potentially many bytes and their values may not be used in arithmetic expressions.
A string is written between double-quotes. It may contain
double-quotes or null characters. The way to get special characters
into a string is to escape these characters: precede them with
a backslash ‘\’ character. For example ‘\\’ represents
one backslash: the first \
is an escape which tells
as to interpret the second character literally as a backslash
(which prevents as from recognizing the second \
as an
escape character). The complete list of escapes follows.
\008
has the value 010, and \009
the value 011.
x
hex-digits...x
works.
Which characters are escapable, and what those escapes represent, varies widely among assemblers. The current set is what we think the BSD 4.2 assembler recognizes, and is a subset of what most C compilers recognize. If you are in doubt, do not use an escape sequence.
A single character may be written as a single quote immediately followed by
that character. Some backslash escapes apply to characters, \b
,
\f
, \n
, \r
, \t
, and \"
with the same meaning
as for strings, plus \'
for a single quote. So if you want to write the
character backslash, you must write '\\ where the first \
escapes
the second \
. As you can see, the quote is an acute accent, not a grave
accent. A newline
immediately following an acute accent is taken as a literal character
and does not count as the end of a statement. The value of a character
constant in a numeric expression is the machine's byte-wide code for
that character. as assumes your character code is ASCII:
'A means 65, 'B means 66, and so on.
as distinguishes three kinds of numbers according to how they
are stored in the target machine. Integers are numbers that
would fit into an int
in the C language. Bignums are
integers, but they are stored in more than 32 bits. Flonums
are floating point numbers, described below.
A binary integer is ‘0b’ or ‘0B’ followed by zero or more of the binary digits ‘01’.
An octal integer is ‘0’ followed by zero or more of the octal digits (‘01234567’).
A decimal integer starts with a non-zero digit followed by zero or more digits (‘0123456789’).
A hexadecimal integer is ‘0x’ or ‘0X’ followed by one or more hexadecimal digits chosen from ‘0123456789abcdefABCDEF’.
Integers have the usual values. To denote a negative integer, use the prefix operator ‘-’ discussed under expressions (see Prefix Operators).
A bignum has the same syntax and semantics as an integer except that the number (or its negative) takes more than 32 bits to represent in binary. The distinction is made because in some places integers are permitted while bignums are not.
A flonum represents a floating point number. The translation is indirect: a decimal floating point number from the text is converted by as to a generic binary floating point number of more than sufficient precision. This generic floating point number is converted to a particular computer's floating point format (or formats) by a portion of as specialized to that computer.
A flonum is written by writing (in order)
On the H8/300 and Renesas / SuperH SH architectures, the letter must be one of the letters ‘DFPRSX’ (in upper or lower case).
On the ARC, the letter must be one of the letters ‘DFRS’ (in upper or lower case).
On the HPPA architecture, the letter must be ‘E’ (upper case only).
At least one of the integer part or the fractional part must be present. The floating point number has the usual base-10 value.
as does all processing using integers. Flonums are computed independently of any floating point hardware in the computer running as.
Roughly, a section is a range of addresses, with no gaps; all data “in” those addresses is treated the same for some particular purpose. For example there may be a “read only” section.
The linker ld
reads many object files (partial programs) and
combines their contents to form a runnable program. When as
emits an object file, the partial program is assumed to start at address 0.
ld
assigns the final addresses for the partial program, so that
different partial programs do not overlap. This is actually an
oversimplification, but it suffices to explain how as uses
sections.
ld
moves blocks of bytes of your program to their run-time
addresses. These blocks slide to their run-time addresses as rigid
units; their length does not change and neither does the order of bytes
within them. Such a rigid unit is called a section. Assigning
run-time addresses to sections is called relocation. It includes
the task of adjusting mentions of object-file addresses so they refer to
the proper run-time addresses.
For the H8/300, and for the Renesas / SuperH SH,
as pads sections if needed to
ensure they end on a word (sixteen bit) boundary.
An object file written by as has at least three sections, any of which may be empty. These are named text, data and bss sections.
When it generates COFF or ELF output,
as can also generate whatever other named sections you specify
using the ‘.section’ directive (see .section
).
If you do not use any directives that place output in the ‘.text’
or ‘.data’ sections, these sections still exist, but are empty.
When as generates SOM or ELF output for the HPPA, as can also generate whatever other named sections you specify using the ‘.space’ and ‘.subspace’ directives. See HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001) for details on the ‘.space’ and ‘.subspace’ assembler directives.
Additionally, as uses different names for the standard text, data, and bss sections when generating SOM output. Program text is placed into the ‘$CODE$’ section, data into ‘$DATA$’, and BSS into ‘$BSS$’.
Within the object file, the text section starts at address 0
, the
data section follows, and the bss section follows the data section.
When generating either SOM or ELF output files on the HPPA, the text
section starts at address 0
, the data section at address
0x4000000
, and the bss section follows the data section.
To let ld
know which data changes when the sections are
relocated, and how to change that data, as also writes to the
object file details of the relocation needed. To perform relocation
ld
must know, each time an address in the object
file is mentioned:
(address) − (start-address of section)?
In fact, every address as ever uses is expressed as
(section) + (offset into section)
Further, most expressions as computes have this section-relative nature. (For some object formats, such as SOM for the HPPA, some expressions are symbol-relative instead.)
In this manual we use the notation {secname N} to mean “offset N into section secname.”
Apart from text, data and bss sections you need to know about the
absolute section. When ld
mixes partial programs,
addresses in the absolute section remain unchanged. For example, address
{absolute 0}
is “relocated” to run-time address 0 by
ld
. Although the linker never arranges two partial programs'
data sections with overlapping addresses after linking, by definition
their absolute sections must overlap. Address {absolute 239}
in one
part of a program is always the same address when the program is running as
address {absolute 239}
in any other part of the program.
The idea of sections is extended to the undefined section. Any address whose section is unknown at assembly time is by definition rendered {undefined U}—where U is filled in later. Since numbers are always defined, the only way to generate an undefined address is to mention an undefined symbol. A reference to a named common block would be such a symbol: its value is unknown at assembly time so it has section undefined.
By analogy the word section is used to describe groups of sections in
the linked program. ld
puts all partial programs' text
sections in contiguous addresses in the linked program. It is
customary to refer to the text section of a program, meaning all
the addresses of all partial programs' text sections. Likewise for
data and bss sections.
Some sections are manipulated by ld
; others are invented for
use of as and have no meaning except during assembly.
ld
deals with just four kinds of sections, summarized below.
ld
treat them as
separate but equal sections. Anything you can say of one section is
true of another.
When the program is running, however, it is
customary for the text section to be unalterable. The
text section is often shared among processes: it contains
instructions, constants and the like. The data section of a running
program is usually alterable: for example, C variables would be stored
in the data section.
ld
must
not change when relocating. In this sense we speak of absolute
addresses being “unrelocatable”: they do not change during relocation.
An idealized example of three relocatable sections follows. The example uses the traditional section names ‘.text’ and ‘.data’. Memory addresses are on the horizontal axis.
+-----+----+--+ partial program # 1: |ttttt|dddd|00| +-----+----+--+ text data bss seg. seg. seg. +---+---+---+ partial program # 2: |TTT|DDD|000| +---+---+---+ +--+---+-----+--+----+---+-----+~~ linked program: | |TTT|ttttt| |dddd|DDD|00000| +--+---+-----+--+----+---+-----+~~ addresses: 0 ...
These sections are meant only for the internal use of as. They have no meaning at run-time. You do not really need to know about these sections for most purposes; but they can be mentioned in as warning messages, so it might be helpful to have an idea of their meanings to as. These sections are used to permit the value of every expression in your assembly language program to be a section-relative address.
Assembled bytes conventionally fall into two sections: text and data. You may have separate groups of data in named sections that you want to end up near to each other in the object file, even though they are not contiguous in the assembler source. as allows you to use subsections for this purpose. Within each section, there can be numbered subsections with values from 0 to 8192. Objects assembled into the same subsection go into the object file together with other objects in the same subsection. For example, a compiler might want to store constants in the text section, but might not want to have them interspersed with the program being assembled. In this case, the compiler could issue a ‘.text 0’ before each section of code being output, and a ‘.text 1’ before each group of constants being output.
Subsections are optional. If you do not use subsections, everything goes in subsection number zero.
Each subsection is zero-padded up to a multiple of four bytes. (Subsections may be padded a different amount on different flavors of as.)
Subsections appear in your object file in numeric order, lowest numbered
to highest. (All this to be compatible with other people's assemblers.)
The object file contains no representation of subsections; ld
and
other programs that manipulate object files see no trace of them.
They just see all your text subsections as a text section, and all your
data subsections as a data section.
To specify which subsection you want subsequent statements assembled
into, use a numeric argument to specify it, in a ‘.text
expression’ or a ‘.data expression’ statement.
When generating COFF output, you
can also use an extra subsection
argument with arbitrary named sections: ‘.section name,
expression’.
When generating ELF output, you
can also use the .subsection
directive (see SubSection)
to specify a subsection: ‘.subsection expression’.
Expression should be an absolute expression
(see Expressions). If you just say ‘.text’ then ‘.text 0’
is assumed. Likewise ‘.data’ means ‘.data 0’. Assembly
begins in text 0
. For instance:
.text 0 # The default subsection is text 0 anyway. .ascii "This lives in the first text subsection. *" .text 1 .ascii "But this lives in the second text subsection." .data 0 .ascii "This lives in the data section," .ascii "in the first data subsection." .text 0 .ascii "This lives in the first text section," .ascii "immediately following the asterisk (*)."
Each section has a location counter incremented by one for every byte
assembled into that section. Because subsections are merely a convenience
restricted to as there is no concept of a subsection location
counter. There is no way to directly manipulate a location counter—but the
.align
directive changes it, and any label definition captures its
current value. The location counter of the section where statements are being
assembled is said to be the active location counter.
The bss section is used for local common variable storage. You may allocate address space in the bss section, but you may not dictate data to load into it before your program executes. When your program starts running, all the contents of the bss section are zeroed bytes.
The .lcomm
pseudo-op defines a symbol in the bss section; see
.lcomm
.
The .comm
pseudo-op may be used to declare a common symbol, which is
another form of uninitialized symbol; see .comm
.
When assembling for a target which supports multiple sections, such as ELF or
COFF, you may switch into the .bss
section and define symbols as usual;
see .section
. You may only assemble zero values into the
section. Typically the section will only contain symbol definitions and
.skip
directives (see .skip
).
Symbols are a central concept: the programmer uses symbols to name things, the linker uses symbols to link, and the debugger uses symbols to debug.
Warning: as does not place symbols in the object file in the same order they were declared. This may break some debuggers.
A label is written as a symbol immediately followed by a colon ‘:’. The symbol then represents the current value of the active location counter, and is, for example, a suitable instruction operand. You are warned if you use the same symbol to represent two different locations: the first definition overrides any other definitions.
On the HPPA, the usual form for a label need not be immediately followed by a
colon, but instead must start in column zero. Only one label may be defined on
a single line. To work around this, the HPPA version of as also
provides a special directive .label
for defining labels more flexibly.
A symbol can be given an arbitrary value by writing a symbol, followed
by an equals sign ‘=’, followed by an expression
(see Expressions). This is equivalent to using the .set
directive. See .set
. In the same way, using a double
equals sign ‘=’‘=’ here represents an equivalent of the
.eqv
directive. See .eqv
.
Blackfin does not support symbol assignment with ‘=’.
Symbol names begin with a letter or with one of ‘._’. On most
machines, you can also use $
in symbol names; exceptions are
noted in Machine Dependencies. That character may be followed by any
string of digits, letters, dollar signs (unless otherwise noted for a
particular target machine), and underscores.
Case of letters is significant: foo
is a different symbol name
than Foo
.
Symbol names do not start with a digit. An exception to this rule is made for Local Labels. See below.
Multibyte characters are supported. To generate a symbol name containing multibyte characters enclose it within double quotes and use escape codes. cf See Strings. Generating a multibyte symbol name from a label is not currently supported.
Each symbol has exactly one name. Each name in an assembly language program refers to exactly one symbol. You may use that symbol name any number of times in a program.
A local symbol is any symbol beginning with certain local label prefixes. By default, the local label prefix is ‘.L’ for ELF systems or ‘L’ for traditional a.out systems, but each target may have its own set of local label prefixes. On the HPPA local symbols begin with ‘L$’.
Local symbols are defined and used within the assembler, but they are normally not saved in object files. Thus, they are not visible when debugging. You may use the ‘-L’ option (see Include Local Symbols) to retain the local symbols in the object files.
Local labels are different from local symbols. Local labels help compilers and programmers use names temporarily. They create symbols which are guaranteed to be unique over the entire scope of the input source code and which can be referred to by a simple notation. To define a local label, write a label of the form ‘N:’ (where N represents any non-negative integer). To refer to the most recent previous definition of that label write ‘Nb’, using the same number as when you defined the label. To refer to the next definition of a local label, write ‘Nf’. The ‘b’ stands for “backwards” and the ‘f’ stands for “forwards”.
There is no restriction on how you can use these labels, and you can reuse them too. So that it is possible to repeatedly define the same local label (using the same number ‘N’), although you can only refer to the most recently defined local label of that number (for a backwards reference) or the next definition of a specific local label for a forward reference. It is also worth noting that the first 10 local labels (‘0:’...‘9:’) are implemented in a slightly more efficient manner than the others.
Here is an example:
1: branch 1f 2: branch 1b 1: branch 2f 2: branch 1b
Which is the equivalent of:
label_1: branch label_3 label_2: branch label_1 label_3: branch label_4 label_4: branch label_3
Local label names are only a notational device. They are immediately transformed into more conventional symbol names before the assembler uses them. The symbol names are stored in the symbol table, appear in error messages, and are optionally emitted to the object file. The names are constructed using these parts:
ld
forget symbols
that start with the local label prefix. These labels are
used for symbols you are never intended to see. If you use the
‘-L’ option then as retains these symbols in the
object file. If you also instruct ld
to retain these symbols,
you may use them in debugging.
So for example, the first 1:
may be named .L1
C-B1
, and
the 44th 3:
may be named .L3
C-B44
.
On some targets as
also supports an even more local form of
local labels called dollar labels. These labels go out of scope (i.e., they
become undefined) as soon as a non-local label is defined. Thus they remain
valid for only a small region of the input source code. Normal local labels,
by contrast, remain in scope for the entire file, or until they are redefined
by another occurrence of the same local label.
Dollar labels are defined in exactly the same way as ordinary local labels, except that they have a dollar sign suffix to their numeric value, e.g., ‘55$:’.
They can also be distinguished from ordinary local labels by their transformed names which use ASCII character ‘\001’ (control-A) as the magic character to distinguish them from ordinary labels. For example, the fifth definition of ‘6$’ may be named ‘.L6C-A5’.
The special symbol ‘.’ refers to the current address that
as is assembling into. Thus, the expression ‘melvin:
.long .’ defines melvin
to contain its own address.
Assigning a value to .
is treated the same as a .org
directive.
Thus, the expression ‘.=.+4’ is the same as saying
‘.space 4’.
Every symbol has, as well as its name, the attributes “Value” and “Type”. Depending on output format, symbols can also have auxiliary attributes.
If you use a symbol without defining it, as assumes zero for all these attributes, and probably won't warn you. This makes the symbol an externally defined symbol, which is generally what you would want.
The value of a symbol is (usually) 32 bits. For a symbol which labels a
location in the text, data, bss or absolute sections the value is the
number of addresses from the start of that section to the label.
Naturally for text, data and bss sections the value of a symbol changes
as ld
changes section base addresses during linking. Absolute
symbols' values do not change during linking: that is why they are
called absolute.
The value of an undefined symbol is treated in a special way. If it is
0 then the symbol is not defined in this assembler source file, and
ld
tries to determine its value from other files linked into the
same program. You make this kind of symbol simply by mentioning a symbol
name without defining it. A non-zero value represents a .comm
common declaration. The value is how much common storage to reserve, in
bytes (addresses). The symbol refers to the first address of the
allocated storage.
The type attribute of a symbol contains relocation (section) information, any flag settings indicating that a symbol is external, and (optionally), other information for linkers and debuggers. The exact format depends on the object-code output format in use.
a.out
This is an arbitrary 16-bit value. You may establish a symbol's
descriptor value by using a .desc
statement
(see .desc
). A descriptor value means nothing to
as.
This is an arbitrary 8-bit value. It means nothing to as.
The COFF format supports a multitude of auxiliary symbol attributes;
like the primary symbol attributes, they are set between .def
and
.endef
directives.
The symbol name is set with .def
; the value and type,
respectively, with .val
and .type
.
The as directives .dim
, .line
, .scl
,
.size
, .tag
, and .weak
can generate auxiliary symbol
table information for COFF.
The SOM format for the HPPA supports a multitude of symbol attributes set with
the .EXPORT
and .IMPORT
directives.
The attributes are described in HP9000 Series 800 Assembly
Language Reference Manual (HP 92432-90001) under the IMPORT
and
EXPORT
assembler directive documentation.
An expression specifies an address or numeric value. Whitespace may precede and/or follow an expression.
The result of an expression must be an absolute number, or else an offset into a particular section. If an expression is not absolute, and there is not enough information when as sees the expression to know its section, a second pass over the source program might be necessary to interpret the expression—but the second pass is currently not implemented. as aborts with an error message in this situation.
An empty expression has no value: it is just whitespace or null. Wherever an absolute expression is required, you may omit the expression, and as assumes a value of (absolute) 0. This is compatible with other assemblers.
An integer expression is one or more arguments delimited by operators.
Arguments are symbols, numbers or subexpressions. In other contexts arguments are sometimes called “arithmetic operands”. In this manual, to avoid confusing them with the “instruction operands” of the machine language, we use the term “argument” to refer to parts of expressions only, reserving the word “operand” to refer only to machine instruction operands.
Symbols are evaluated to yield {section NNN} where section is one of text, data, bss, absolute, or undefined. NNN is a signed, 2's complement 32 bit integer.
Numbers are usually integers.
A number can be a flonum or bignum. In this case, you are warned that only the low order 32 bits are used, and as pretends these 32 bits are an integer. You may write integer-manipulating instructions that act on exotic constants, compatible with other assemblers.
Subexpressions are a left parenthesis ‘(’ followed by an integer expression, followed by a right parenthesis ‘)’; or a prefix operator followed by an argument.
Operators are arithmetic functions, like +
or %
. Prefix
operators are followed by an argument. Infix operators appear
between their arguments. Operators may be preceded and/or followed by
whitespace.
as has the following prefix operators. They each take one argument, which must be absolute.
-
~
Infix operators take two arguments, one on either side. Operators
have precedence, but operations with equal precedence are performed left
to right. Apart from +
or -, both arguments must be
absolute, and the result is absolute.
*
/
%
<<
>>
|
&
^
!
+
-
==
<>
!=
<
>
>=
<=
The comparison operators can be used as infix operators. A true results has a value of -1 whereas a false result has a value of 0. Note, these operators perform signed comparisons.
&&
||
These two logical operations can be used to combine the results of sub expressions. Note, unlike the comparison operators a true result returns a value of 1 but a false results does still return 0. Also note that the logical or operator has a slightly lower precedence than logical and.
In short, it's only meaningful to add or subtract the offsets in an address; you can only have a defined section in one of the two arguments.
All assembler directives have names that begin with a period (‘.’). The names are case insensitive for most targets, and usually written in lower case.
This chapter discusses directives that are available regardless of the target machine configuration for the gnu assembler. Some machine configurations provide additional directives. See Machine Dependencies.
.abort
This directive stops the assembly immediately. It is for
compatibility with other assemblers. The original idea was that the
assembly language source would be piped into the assembler. If the sender
of the source quit, it could use this directive tells as to
quit also. One day .abort
will not be supported.
.ABORT
(COFF)When producing COFF output, as accepts this directive as a synonym for ‘.abort’.
.align
abs-expr,
abs-expr,
abs-exprPad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the alignment required, as described below.
The second expression (also absolute) gives the fill value to be stored in the padding bytes. It (and the comma) may be omitted. If it is omitted, the padding bytes are normally zero. However, on most systems, if the section is marked as containing code and the fill value is omitted, the space is filled with no-op instructions.
The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by this alignment directive. If doing the alignment would require skipping more bytes than the specified maximum, then the alignment is not done at all. You can omit the fill value (the second argument) entirely by simply using two commas after the required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate.
The way the required alignment is specified varies from system to system. For the arc, hppa, i386 using ELF, iq2000, m68k, or1k, s390, sparc, tic4x, tic80 and xtensa, the first expression is the alignment request in bytes. For example ‘.align 8’ advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed. For the tic54x, the first expression is the alignment request in words.
For other systems, including ppc, i386 using a.out format, arm and strongarm, it is the number of low-order zero bits the location counter must have after advancement. For example ‘.align 3’ advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed.
This inconsistency is due to the different behaviors of the various
native assemblers for these systems which GAS must emulate.
GAS also provides .balign
and .p2align
directives,
described later, which have a consistent behavior across all
architectures (but are specific to GAS).
.altmacro
Enable alternate macro mode, enabling:
LOCAL
name [ , ... ]
LOCAL
, is available. It is used to
generate a string replacement for each of the name arguments, and
replace any instances of name in each macro expansion. The
replacement string is unique in the assembly, and different for each
separate macro expansion. LOCAL
allows you to write macros that
define symbols, without fear of conflict between separate macro expansions.
String delimiters
"
string"
:
'
string'
<
string>
single-character string escape
Expression results as strings
.ascii "
string"
....ascii
expects zero or more string literals (see Strings)
separated by commas. It assembles each string (with no automatic
trailing zero byte) into consecutive addresses.
.asciz "
string"
....asciz
is just like .ascii
, but each string is followed by
a zero byte. The “z” in ‘.asciz’ stands for “zero”.
.balign[wl]
abs-expr,
abs-expr,
abs-exprPad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the alignment request in bytes. For example ‘.balign 8’ advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed.
The second expression (also absolute) gives the fill value to be stored in the padding bytes. It (and the comma) may be omitted. If it is omitted, the padding bytes are normally zero. However, on most systems, if the section is marked as containing code and the fill value is omitted, the space is filled with no-op instructions.
The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by this alignment directive. If doing the alignment would require skipping more bytes than the specified maximum, then the alignment is not done at all. You can omit the fill value (the second argument) entirely by simply using two commas after the required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate.
The .balignw
and .balignl
directives are variants of the
.balign
directive. The .balignw
directive treats the fill
pattern as a two byte word value. The .balignl
directives treats the
fill pattern as a four byte longword value. For example, .balignw
4,0x368d
will align to a multiple of 4. If it skips two bytes, they will be
filled in with the value 0x368d (the exact placement of the bytes depends upon
the endianness of the processor). If it skips 1 or 3 bytes, the fill value is
undefined.
.bundle_align_mode
abs-expr.bundle_align_mode
enables or disables aligned instruction
bundle mode. In this mode, sequences of adjacent instructions are grouped
into fixed-sized bundles. If the argument is zero, this mode is
disabled (which is the default state). If the argument it not zero, it
gives the size of an instruction bundle as a power of two (as for the
.p2align
directive, see P2align).
For some targets, it's an ABI requirement that no instruction may span a
certain aligned boundary. A bundle is simply a sequence of
instructions that starts on an aligned boundary. For example, if
abs-expr is 5
then the bundle size is 32, so each aligned
chunk of 32 bytes is a bundle. When aligned instruction bundle mode is in
effect, no single instruction may span a boundary between bundles. If an
instruction would start too close to the end of a bundle for the length of
that particular instruction to fit within the bundle, then the space at the
end of that bundle is filled with no-op instructions so the instruction
starts in the next bundle. As a corollary, it's an error if any single
instruction's encoding is longer than the bundle size.
.bundle_lock
and .bundle_unlock
The .bundle_lock
and directive .bundle_unlock
directives
allow explicit control over instruction bundle padding. These directives
are only valid when .bundle_align_mode
has been used to enable
aligned instruction bundle mode. It's an error if they appear when
.bundle_align_mode
has not been used at all, or when the last
directive was .bundle_align_mode 0
.
For some targets, it's an ABI requirement that certain instructions may
appear only as part of specified permissible sequences of multiple
instructions, all within the same bundle. A pair of .bundle_lock
and .bundle_unlock
directives define a bundle-locked
instruction sequence. For purposes of aligned instruction bundle mode, a
sequence starting with .bundle_lock
and ending with
.bundle_unlock
is treated as a single instruction. That is, the
entire sequence must fit into a single bundle and may not span a bundle
boundary. If necessary, no-op instructions will be inserted before the
first instruction of the sequence so that the whole sequence starts on an
aligned bundle boundary. It's an error if the sequence is longer than the
bundle size.
For convenience when using .bundle_lock
and .bundle_unlock
inside assembler macros (see Macro), bundle-locked sequences may be
nested. That is, a second .bundle_lock
directive before the next
.bundle_unlock
directive has no effect except that it must be
matched by another closing .bundle_unlock
so that there is the
same number of .bundle_lock
and .bundle_unlock
directives.
.byte
expressions.byte
expects zero or more expressions, separated by commas.
Each expression is assembled into the next byte.
.cfi_sections
section_list.cfi_sections
may be used to specify whether CFI directives
should emit .eh_frame
section and/or .debug_frame
section.
If section_list is .eh_frame
, .eh_frame
is emitted,
if section_list is .debug_frame
, .debug_frame
is emitted.
To emit both use .eh_frame, .debug_frame
. The default if this
directive is not used is .cfi_sections .eh_frame
.
On targets that support compact unwinding tables these can be generated
by specifying .eh_frame_entry
instead of .eh_frame
.
Some targets may support an additional name, such as .c6xabi.exidx
which is used by the target.
The .cfi_sections
directive can be repeated, with the same or different
arguments, provided that CFI generation has not yet started. Once CFI
generation has started however the section list is fixed and any attempts to
redefine it will result in an error.
.cfi_startproc [simple]
.cfi_startproc
is used at the beginning of each function that
should have an entry in .eh_frame
. It initializes some internal
data structures. Don't forget to close the function by
.cfi_endproc
.
Unless .cfi_startproc
is used along with parameter simple
it also emits some architecture dependent initial CFI instructions.
.cfi_endproc
.cfi_endproc
is used at the end of a function where it closes its
unwind entry previously opened by
.cfi_startproc
, and emits it to .eh_frame
.
.cfi_personality
encoding [,
exp]
.cfi_personality
defines personality routine and its encoding.
encoding must be a constant determining how the personality
should be encoded. If it is 255 (DW_EH_PE_omit
), second
argument is not present, otherwise second argument should be
a constant or a symbol name. When using indirect encodings,
the symbol provided should be the location where personality
can be loaded from, not the personality routine itself.
The default after .cfi_startproc
is .cfi_personality 0xff
,
no personality routine.
.cfi_personality_id
idcfi_personality_id
defines a personality routine by its index as
defined in a compact unwinding format.
Only valid when generating compact EH frames (i.e.
with .cfi_sections eh_frame_entry
.
.cfi_fde_data [
opcode1 [, ...]]
cfi_fde_data
is used to describe the compact unwind opcodes to be
used for the current function. These are emitted inline in the
.eh_frame_entry
section if small enough and there is no LSDA, or
in the .gnu.extab
section otherwise.
Only valid when generating compact EH frames (i.e.
with .cfi_sections eh_frame_entry
.
.cfi_lsda
encoding [,
exp]
.cfi_lsda
defines LSDA and its encoding.
encoding must be a constant determining how the LSDA
should be encoded. If it is 255 (DW_EH_PE_omit
), the second
argument is not present, otherwise the second argument should be a constant
or a symbol name. The default after .cfi_startproc
is .cfi_lsda 0xff
,
meaning that no LSDA is present.
.cfi_inline_lsda
[align].cfi_inline_lsda
marks the start of a LSDA data section and
switches to the corresponding .gnu.extab
section.
Must be preceded by a CFI block containing a .cfi_lsda
directive.
Only valid when generating compact EH frames (i.e.
with .cfi_sections eh_frame_entry
.
The table header and unwinding opcodes will be generated at this point,
so that they are immediately followed by the LSDA data. The symbol
referenced by the .cfi_lsda
directive should still be defined
in case a fallback FDE based encoding is used. The LSDA data is terminated
by a section directive.
The optional align argument specifies the alignment required.
The alignment is specified as a power of two, as with the
.p2align
directive.
.cfi_def_cfa
register,
offset.cfi_def_cfa
defines a rule for computing CFA as: take
address from register and add offset to it.
.cfi_def_cfa_register
register.cfi_def_cfa_register
modifies a rule for computing CFA. From
now on register will be used instead of the old one. Offset
remains the same.
.cfi_def_cfa_offset
offset.cfi_def_cfa_offset
modifies a rule for computing CFA. Register
remains the same, but offset is new. Note that it is the
absolute offset that will be added to a defined register to compute
CFA address.
.cfi_adjust_cfa_offset
offsetSame as .cfi_def_cfa_offset
but offset is a relative
value that is added/subtracted from the previous offset.
.cfi_offset
register,
offsetPrevious value of register is saved at offset offset from CFA.
.cfi_val_offset
register,
offsetPrevious value of register is CFA + offset.
.cfi_rel_offset
register,
offsetPrevious value of register is saved at offset offset from
the current CFA register. This is transformed to .cfi_offset
using the known displacement of the CFA register from the CFA.
This is often easier to use, because the number will match the
code it's annotating.
.cfi_register
register1,
register2Previous value of register1 is saved in register register2.
.cfi_restore
register.cfi_restore
says that the rule for register is now the
same as it was at the beginning of the function, after all initial
instruction added by .cfi_startproc
were executed.
.cfi_undefined
registerFrom now on the previous value of register can't be restored anymore.
.cfi_same_value
registerCurrent value of register is the same like in the previous frame, i.e. no restoration needed.
.cfi_remember_state
and .cfi_restore_state
.cfi_remember_state
pushes the set of rules for every register onto an
implicit stack, while .cfi_restore_state
pops them off the stack and
places them in the current row. This is useful for situations where you have
multiple .cfi_*
directives that need to be undone due to the control
flow of the program. For example, we could have something like this (assuming
the CFA is the value of rbp
):
je label popq %rbx .cfi_restore %rbx popq %r12 .cfi_restore %r12 popq %rbp .cfi_restore %rbp .cfi_def_cfa %rsp, 8 ret label: /* Do something else */
Here, we want the .cfi
directives to affect only the rows corresponding
to the instructions before label
. This means we'd have to add multiple
.cfi
directives after label
to recreate the original save
locations of the registers, as well as setting the CFA back to the value of
rbp
. This would be clumsy, and result in a larger binary size. Instead,
we can write:
je label popq %rbx .cfi_remember_state .cfi_restore %rbx popq %r12 .cfi_restore %r12 popq %rbp .cfi_restore %rbp .cfi_def_cfa %rsp, 8 ret label: .cfi_restore_state /* Do something else */
That way, the rules for the instructions after label
will be the same
as before the first .cfi_restore
without having to use multiple
.cfi
directives.
.cfi_return_column
registerChange return column register, i.e. the return address is either directly in register or can be accessed by rules for register.
.cfi_signal_frame
Mark current function as signal trampoline.
.cfi_window_save
SPARC register window has been saved.
.cfi_escape
expression[, ...]Allows the user to add arbitrary bytes to the unwind info. One might use this to add OS-specific CFI opcodes, or generic CFI opcodes that GAS does not yet support.
.cfi_val_encoded_addr
register,
encoding,
labelThe current value of register is label. The value of label
will be encoded in the output file according to encoding; see the
description of .cfi_personality
for details on this encoding.
The usefulness of equating a register to a fixed label is probably limited to the return address register. Here, it can be useful to mark a code segment that has only one return address which is reached by a direct branch and no copy of the return address exists in memory or another register.
.comm
symbol ,
length .comm
declares a common symbol named symbol. When linking, a
common symbol in one object file may be merged with a defined or common symbol
of the same name in another object file. If ld
does not see a
definition for the symbol–just one or more common symbols–then it will
allocate length bytes of uninitialized memory. length must be an
absolute expression. If ld
sees multiple common symbols with
the same name, and they do not all have the same size, it will allocate space
using the largest size.
When using ELF or (as a GNU extension) PE, the .comm
directive takes
an optional third argument. This is the desired alignment of the symbol,
specified for ELF as a byte boundary (for example, an alignment of 16 means
that the least significant 4 bits of the address should be zero), and for PE
as a power of two (for example, an alignment of 5 means aligned to a 32-byte
boundary). The alignment must be an absolute expression, and it must be a
power of two. If ld
allocates uninitialized memory for the
common symbol, it will use the alignment when placing the symbol. If no
alignment is specified, as will set the alignment to the
largest power of two less than or equal to the size of the symbol, up to a
maximum of 16 on ELF, or the default section alignment of 4 on PE1.
The syntax for .comm
differs slightly on the HPPA. The syntax is
‘symbol .comm, length’; symbol is optional.
.data
subsection
.data
tells as to assemble the following statements onto the
end of the data subsection numbered subsection (which is an
absolute expression). If subsection is omitted, it defaults
to zero.
.dc[
size]
expressions
The .dc
directive expects zero or more expressions separated by
commas. These expressions are evaluated and their values inserted into the
current section. The size of the emitted value depends upon the suffix to the
.dc
directive:
‘
.a’
‘
.b’
‘
.d’
‘
.l’
‘
.s’
‘
.w’
.word
directive would emit
32-bit values.
‘
.x’
If no suffix is used then ‘.w’ is assumed.
The byte ordering is target dependent, as is the size and format of floating point values.
.dcb[
size]
number [,
fill]
This directive emits number copies of fill, each of size bytes. Both number and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero. The size suffix, if present, must be one of:
‘
.b’
‘
.d’
‘
.l’
‘
.s’
‘
.w’
‘
.x’
If the size suffix is omitted then ‘.w’ is assumed.
The byte ordering is target dependent, as is the size and format of floating point values.
.ds[
size]
number [,
fill]
This directive emits number copies of fill, each of size bytes. Both number and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero. The size suffix, if present, must be one of:
‘
.b’
‘
.d’
‘
.l’
‘
.p’
‘
.s’
‘
.w’
‘
.x’
Note - unlike the .dcb
directive the ‘.d’, ‘.s’ and ‘.x’
suffixes do not indicate that floating-point values are to be inserted.
If the size suffix is omitted then ‘.w’ is assumed.
The byte ordering is target dependent.
.def
nameBegin defining debugging information for a symbol name; the
definition extends until the .endef
directive is encountered.
.desc
symbol,
abs-expressionThis directive sets the descriptor of the symbol (see Symbol Attributes) to the low 16 bits of an absolute expression.
The ‘.desc’ directive is not available when as is
configured for COFF output; it is only for a.out
or b.out
object format. For the sake of compatibility, as accepts
it, but produces no output, when configured for COFF.
.dim
This directive is generated by compilers to include auxiliary debugging
information in the symbol table. It is only permitted inside
.def
/.endef
pairs.
.double
flonums.double
expects zero or more flonums, separated by commas. It
assembles floating point numbers.
The exact kind of floating point numbers emitted depends on how
as is configured. See Machine Dependencies.
.eject
Force a page break at this point, when generating assembly listings.
.else
.else
is part of the as support for conditional
assembly; see .if
. It marks the beginning of a section
of code to be assembled if the condition for the preceding .if
was false.
.elseif
.elseif
is part of the as support for conditional
assembly; see .if
. It is shorthand for beginning a new
.if
block that would otherwise fill the entire .else
section.
.end
.end
marks the end of the assembly file. as does not
process anything in the file past the .end
directive.
.endef
This directive flags the end of a symbol definition begun with
.def
.
.endfunc
.endfunc
marks the end of a function specified with .func
.
.endif
.endif
is part of the as support for conditional assembly;
it marks the end of a block of code that is only assembled
conditionally. See .if
.
.equ
symbol,
expressionThis directive sets the value of symbol to expression.
It is synonymous with ‘.set’; see .set
.
The syntax for equ
on the HPPA is
‘symbol .equ expression’.
The syntax for equ
on the Z80 is
‘symbol equ expression’.
On the Z80 it is an error if symbol is already defined,
but the symbol is not protected from later redefinition.
Compare Equiv.
.equiv
symbol,
expressionThe .equiv
directive is like .equ
and .set
, except that
the assembler will signal an error if symbol is already defined. Note a
symbol which has been referenced but not actually defined is considered to be
undefined.
Except for the contents of the error message, this is roughly equivalent to
.ifdef SYM .err .endif .equ SYM,VAL
plus it protects the symbol from later redefinition.
.eqv
symbol,
expressionThe .eqv
directive is like .equiv
, but no attempt is made to
evaluate the expression or any part of it immediately. Instead each time
the resulting symbol is used in an expression, a snapshot of its current
value is taken.
.err
If as assembles a .err
directive, it will print an error
message and, unless the -Z option was used, it will not generate an
object file. This can be used to signal an error in conditionally compiled code.
.error "
string"
Similarly to .err
, this directive emits an error, but you can specify a
string that will be emitted as the error message. If you don't specify the
message, it defaults to ".error directive invoked in source file"
.
See Error and Warning Messages.
.error "This code has not been assembled and tested."
.exitm
Exit early from the current macro definition. See Macro.
.extern
.extern
is accepted in the source program—for compatibility
with other assemblers—but it is ignored. as treats
all undefined symbols as external.
.fail
expressionGenerates an error or a warning. If the value of the expression is 500 or more, as will print a warning message. If the value is less than 500, as will print an error message. The message will include the value of expression. This can occasionally be useful inside complex nested macros or conditional assembly.
.file
There are two different versions of the .file
directive. Targets
that support DWARF2 line number information use the DWARF2 version of
.file
. Other targets use the default version.
This version of the .file
directive tells as that we
are about to start a new logical file. The syntax is:
.file string
string is the new file name. In general, the filename is
recognized whether or not it is surrounded by quotes ‘"’; but if you wish
to specify an empty file name, you must give the quotes–""
. This
statement may go away in future: it is only recognized to be compatible with
old as programs.
When emitting DWARF2 line number information, .file
assigns filenames
to the .debug_line
file name table. The syntax is:
.file fileno filename
The fileno operand should be a unique positive integer to use as the index of the entry in the table. The filename operand is a C string literal.
The detail of filename indices is exposed to the user because the filename
table is shared with the .debug_info
section of the DWARF2 debugging
information, and thus the user must know the exact indices that table
entries will have.
.fill
repeat ,
size ,
valuerepeat, size and value are absolute expressions. This emits repeat copies of size bytes. Repeat may be zero or more. Size may be zero or more, but if it is more than 8, then it is deemed to have the value 8, compatible with other people's assemblers. The contents of each repeat bytes is taken from an 8-byte number. The highest order 4 bytes are zero. The lowest order 4 bytes are value rendered in the byte-order of an integer on the computer as is assembling for. Each size bytes in a repetition is taken from the lowest order size bytes of this number. Again, this bizarre behavior is compatible with other people's assemblers.
size and value are optional. If the second comma and value are absent, value is assumed zero. If the first comma and following tokens are absent, size is assumed to be 1.
.float
flonumsThis directive assembles zero or more flonums, separated by commas. It
has the same effect as .single
.
The exact kind of floating point numbers emitted depends on how
as is configured.
See Machine Dependencies.
.func
name[,
label]
.func
emits debugging information to denote function name, and
is ignored unless the file is assembled with debugging enabled.
Only ‘--gstabs[+]’ is currently supported.
label is the entry point of the function and if omitted name
prepended with the ‘leading char’ is used.
‘leading char’ is usually _
or nothing, depending on the target.
All functions are currently defined to have void
return type.
The function must be terminated with .endfunc
.
.global
symbol, .globl
symbol.global
makes the symbol visible to ld
. If you define
symbol in your partial program, its value is made available to
other partial programs that are linked with it. Otherwise,
symbol takes its attributes from a symbol of the same name
from another file linked into the same program.
Both spellings (‘.globl’ and ‘.global’) are accepted, for compatibility with other assemblers.
On the HPPA, .global
is not always enough to make it accessible to other
partial programs. You may need the HPPA-only .EXPORT
directive as well.
See HPPA Assembler Directives.
.gnu_attribute
tag,
valueRecord a gnu object attribute for this file. See Object Attributes.
.hidden
namesThis is one of the ELF visibility directives. The other two are
.internal
(see .internal
) and
.protected
(see .protected
).
This directive overrides the named symbols default visibility (which is set by
their binding: local, global or weak). The directive sets the visibility to
hidden
which means that the symbols are not visible to other components.
Such symbols are always considered to be protected
as well.
.hword
expressionsThis expects zero or more expressions, and emits a 16 bit number for each.
This directive is a synonym for ‘.short’; depending on the target architecture, it may also be a synonym for ‘.word’.
.ident
This directive is used by some assemblers to place tags in object files. The
behavior of this directive varies depending on the target. When using the
a.out object file format, as simply accepts the directive for
source-file compatibility with existing assemblers, but does not emit anything
for it. When using COFF, comments are emitted to the .comment
or
.rdata
section, depending on the target. When using ELF, comments are
emitted to the .comment
section.
.if
absolute expression.if
marks the beginning of a section of code which is only
considered part of the source program being assembled if the argument
(which must be an absolute expression) is non-zero. The end of
the conditional section of code must be marked by .endif
(see .endif
); optionally, you may include code for the
alternative condition, flagged by .else
(see .else
).
If you have several conditions to check, .elseif
may be used to avoid
nesting blocks if/else within each subsequent .else
block.
The following variants of .if
are also supported:
.ifdef
symbol.ifb
text.ifc
string1,
string2.ifeq
absolute expression.ifeqs
string1,
string2.ifc
. The strings must be quoted using double quotes.
.ifge
absolute expression.ifgt
absolute expression.ifle
absolute expression.iflt
absolute expression.ifnb
text.ifb
, but the sense of the test is reversed: this assembles the
following section of code if the operand is non-blank (non-empty).
.ifnc
string1,
string2.
.ifc
, but the sense of the test is reversed: this assembles the
following section of code if the two strings are not the same.
.ifndef
symbol.ifnotdef
symbol.ifne
absolute expression.if
).
.ifnes
string1,
string2.ifeqs
, but the sense of the test is reversed: this assembles the
following section of code if the two strings are not the same.
.incbin "
file"[,
skip[,
count]]
The incbin
directive includes file verbatim at the current
location. You can control the search paths used with the ‘-I’ command-line
option (see Command-Line Options). Quotation marks are required
around file.
The skip argument skips a number of bytes from the start of the
file. The count argument indicates the maximum number of bytes to
read. Note that the data is not aligned in any way, so it is the user's
responsibility to make sure that proper alignment is provided both before and
after the incbin
directive.
.include "
file"
This directive provides a way to include supporting files at specified
points in your source program. The code from file is assembled as
if it followed the point of the .include
; when the end of the
included file is reached, assembly of the original file continues. You
can control the search paths used with the ‘-I’ command-line option
(see Command-Line Options). Quotation marks are required
around file.
.int
expressionsExpect zero or more expressions, of any section, separated by commas. For each expression, emit a number that, at run time, is the value of that expression. The byte order and bit size of the number depends on what kind of target the assembly is for.
.internal
namesThis is one of the ELF visibility directives. The other two are
.hidden
(see .hidden
) and
.protected
(see .protected
).
This directive overrides the named symbols default visibility (which is set by
their binding: local, global or weak). The directive sets the visibility to
internal
which means that the symbols are considered to be hidden
(i.e., not visible to other components), and that some extra, processor specific
processing must also be performed upon the symbols as well.
.irp
symbol,
values...Evaluate a sequence of statements assigning different values to symbol.
The sequence of statements starts at the .irp
directive, and is
terminated by an .endr
directive. For each value, symbol is
set to value, and the sequence of statements is assembled. If no
value is listed, the sequence of statements is assembled once, with
symbol set to the null string. To refer to symbol within the
sequence of statements, use \symbol.
For example, assembling
.irp param,1,2,3 move d\param,sp@- .endr
is equivalent to assembling
move d1,sp@- move d2,sp@- move d3,sp@-
For some caveats with the spelling of symbol, see also Macro.
.irpc
symbol,
values...Evaluate a sequence of statements assigning different values to symbol.
The sequence of statements starts at the .irpc
directive, and is
terminated by an .endr
directive. For each character in value,
symbol is set to the character, and the sequence of statements is
assembled. If no value is listed, the sequence of statements is
assembled once, with symbol set to the null string. To refer to
symbol within the sequence of statements, use \symbol.
For example, assembling
.irpc param,123 move d\param,sp@- .endr
is equivalent to assembling
move d1,sp@- move d2,sp@- move d3,sp@-
For some caveats with the spelling of symbol, see also the discussion at See Macro.
.lcomm
symbol ,
lengthReserve length (an absolute expression) bytes for a local common
denoted by symbol. The section and value of symbol are
those of the new local common. The addresses are allocated in the bss
section, so that at run-time the bytes start off zeroed. Symbol
is not declared global (see .global
), so is normally
not visible to ld
.
Some targets permit a third argument to be used with .lcomm
. This
argument specifies the desired alignment of the symbol in the bss section.
The syntax for .lcomm
differs slightly on the HPPA. The syntax is
‘symbol .lcomm, length’; symbol is optional.
.lflags
as accepts this directive, for compatibility with other assemblers, but ignores it.
.line
line-numberChange the logical line number. line-number must be an absolute expression. The next line has that logical line number. Therefore any other statements on the current line (after a statement separator character) are reported as on logical line number line-number − 1. One day as will no longer support this directive: it is recognized only for compatibility with existing assembler programs.
Even though this is a directive associated with the a.out
or
b.out
object-code formats, as still recognizes it
when producing COFF output, and treats ‘.line’ as though it
were the COFF ‘.ln’ if it is found outside a
.def
/.endef
pair.
Inside a .def
, ‘.line’ is, instead, one of the directives
used by compilers to generate auxiliary symbol information for
debugging.
.linkonce [
type]
Mark the current section so that the linker only includes a single copy of it.
This may be used to include the same section in several different object files,
but ensure that the linker will only include it once in the final output file.
The .linkonce
pseudo-op must be used for each instance of the section.
Duplicate sections are detected based on the section name, so it should be
unique.
This directive is only supported by a few object file formats; as of this writing, the only object file format which supports it is the Portable Executable format used on Windows NT.
The type argument is optional. If specified, it must be one of the following strings. For example:
.linkonce same_size
Not all types may be supported on all object file formats.
discard
one_only
same_size
same_contents
.list
Control (in conjunction with the .nolist
directive) whether or
not assembly listings are generated. These two directives maintain an
internal counter (which is zero initially). .list
increments the
counter, and .nolist
decrements it. Assembly listings are
generated whenever the counter is greater than zero.
By default, listings are disabled. When you enable them (with the ‘-a’ command-line option; see Command-Line Options), the initial value of the listing counter is one.
.ln
line-number‘.ln’ is a synonym for ‘.line’.
.loc
fileno lineno [
column] [
options]
When emitting DWARF2 line number information,
the .loc
directive will add a row to the .debug_line
line
number matrix corresponding to the immediately following assembly
instruction. The fileno, lineno, and optional column
arguments will be applied to the .debug_line
state machine before
the row is added.
The options are a sequence of the following tokens in any order:
basic_block
basic_block
register in the
.debug_line
state machine to true
.
prologue_end
prologue_end
register in the
.debug_line
state machine to true
.
epilogue_begin
epilogue_begin
register in the
.debug_line
state machine to true
.
is_stmt
valueis_stmt
register in the
.debug_line
state machine to value
, which must be
either 0 or 1.
isa
valueisa
register in the .debug_line
state machine to value, which must be an unsigned integer.
discriminator
valuediscriminator
register in the .debug_line
state machine to value, which must be an unsigned integer.
view
value.debug_line
in reference to the
current address (which might not be the same as that of the following assembly
instruction), and to associate value with the view
register in the
.debug_line
state machine. If value is a label, both the
view
register and the label are set to the number of prior .loc
directives at the same program location. If value is the literal
0
, the view
register is set to zero, and the assembler asserts
that there aren't any prior .loc
directives at the same program
location. If value is the literal -0
, the assembler arrange for
the view
register to be reset in this row, even if there are prior
.loc
directives at the same program location.
.loc_mark_labels
enableWhen emitting DWARF2 line number information,
the .loc_mark_labels
directive makes the assembler emit an entry
to the .debug_line
line number matrix with the basic_block
register in the state machine set whenever a code label is seen.
The enable argument should be either 1 or 0, to enable or disable
this function respectively.
.local
namesThis directive, which is available for ELF targets, marks each symbol in
the comma-separated list of names
as a local symbol so that it
will not be externally visible. If the symbols do not already exist,
they will be created.
For targets where the .lcomm
directive (see Lcomm) does not
accept an alignment argument, which is the case for most ELF targets,
the .local
directive can be used in combination with .comm
(see Comm) to define aligned local common data.
.long
expressions.long
is the same as ‘.int’. See .int
.
.macro
The commands .macro
and .endm
allow you to define macros that
generate assembly output. For example, this definition specifies a macro
sum
that puts a sequence of numbers into memory:
.macro sum from=0, to=5 .long \from .if \to-\from sum "(\from+1)",\to .endif .endm
With that definition, ‘SUM 0,5’ is equivalent to this assembly input:
.long 0 .long 1 .long 2 .long 3 .long 4 .long 5
.macro
macname.macro
macname macargs ...
req
’), or whether it takes all of the remaining arguments
(through ‘:vararg
’). You can supply a default value for any
macro argument by following the name with ‘=deflt’. You
cannot define two macros with the same macname unless it has been
subject to the .purgem
directive (see Purgem) between the two
definitions. For example, these are all valid .macro
statements:
.macro comm
comm
, which takes no
arguments.
.macro plus1 p, p1
.macro plus1 p p1
plus1
,
which takes two arguments; within the macro definition, write
‘\p’ or ‘\p1’ to evaluate the arguments.
.macro reserve_str p1=0 p2
reserve_str
, with two
arguments. The first argument has a default value, but not the second.
After the definition is complete, you can call the macro either as
‘reserve_str a,b’ (with ‘\p1’ evaluating to
a and ‘\p2’ evaluating to b), or as ‘reserve_str
,b’ (with ‘\p1’ evaluating as the default, in this case
‘0’, and ‘\p2’ evaluating to b).
.macro m p1:req, p2=0, p3:vararg
m
, with at least three
arguments. The first argument must always have a value specified, but
not the second, which instead has a default value. The third formal
will get assigned all remaining arguments specified at invocation time.
When you call a macro, you can specify the argument values either by position, or by keyword. For example, ‘sum 9,17’ is equivalent to ‘sum to=17, from=9’.
Note that since each of the macargs can be an identifier exactly
as any other one permitted by the target architecture, there may be
occasional problems if the target hand-crafts special meanings to certain
characters when they occur in a special position. For example, if the colon
(:
) is generally permitted to be part of a symbol name, but the
architecture specific code special-cases it when occurring as the final
character of a symbol (to denote a label), then the macro parameter
replacement code will have no way of knowing that and consider the whole
construct (including the colon) an identifier, and check only this
identifier for being the subject to parameter substitution. So for example
this macro definition:
.macro label l \l: .endm
might not work as expected. Invoking ‘label foo’ might not create a label called ‘foo’ but instead just insert the text ‘\l:’ into the assembler source, probably generating an error about an unrecognised identifier.
Similarly problems might occur with the period character (‘.’) which is often allowed inside opcode names (and hence identifier names). So for example constructing a macro to build an opcode from a base name and a length specifier like this:
.macro opcode base length \base.\length .endm
and invoking it as ‘opcode store l’ will not create a ‘store.l’ instruction but instead generate some kind of error as the assembler tries to interpret the text ‘\base.\length’.
There are several possible ways around this problem:
Insert white space
.macro label l \l : .endm
Use ‘
\()’
.macro opcode base length \base\().\length .endm
Use the alternate macro syntax mode
.altmacro .macro label l l&: .endm
Note: this problem of correctly identifying string parameters to pseudo ops
also applies to the identifiers used in .irp
(see Irp)
and .irpc
(see Irpc) as well.
.endm
.exitm
\@
LOCAL
name [ , ... ]
LOCAL
is only available if you select “alternate
macro syntax” with ‘--alternate’ or .altmacro
.
See .altmacro
.
.mri
valIf val is non-zero, this tells as to enter MRI mode. If
val is zero, this tells as to exit MRI mode. This change
affects code assembled until the next .mri
directive, or until the end
of the file. See MRI mode.
.noaltmacro
Disable alternate macro mode. See Altmacro.
.nolist
Control (in conjunction with the .list
directive) whether or
not assembly listings are generated. These two directives maintain an
internal counter (which is zero initially). .list
increments the
counter, and .nolist
decrements it. Assembly listings are
generated whenever the counter is greater than zero.
.nops
size[,
control]
This directive emits size bytes filled with no-op instructions. size is absolute expression, which must be a positve value. control controls how no-op instructions should be generated. If the comma and control are omitted, control is assumed to be zero.
Note: For Intel 80386 and AMD x86-64 targets, control specifies the size limit of a no-op instruction. The valid values of control are between 0 and 4 in 16-bit mode, between 0 and 7 when tuning for older processors in 32-bit mode, between 0 and 11 in 64-bit mode or when tuning for newer processors in 32-bit mode. When 0 is used, the no-op instruction size limit is set to the maximum supported size.
.octa
bignumsThis directive expects zero or more bignums, separated by commas. For each bignum, it emits a 16-byte integer.
The term “octa” comes from contexts in which a “word” is two bytes; hence octa-word for 16 bytes.
.offset
locSet the location counter to loc in the absolute section. loc must
be an absolute expression. This directive may be useful for defining
symbols with absolute values. Do not confuse it with the .org
directive.
.org
new-lc ,
fillAdvance the location counter of the current section to
new-lc. new-lc is either an absolute expression or an
expression with the same section as the current subsection. That is,
you can't use .org
to cross sections: if new-lc has the
wrong section, the .org
directive is ignored. To be compatible
with former assemblers, if the section of new-lc is absolute,
as issues a warning, then pretends the section of new-lc
is the same as the current subsection.
.org
may only increase the location counter, or leave it
unchanged; you cannot use .org
to move the location counter
backwards.
Because as tries to assemble programs in one pass, new-lc may not be undefined. If you really detest this restriction we eagerly await a chance to share your improved assembler.
Beware that the origin is relative to the start of the section, not to the start of the subsection. This is compatible with other people's assemblers.
When the location counter (of the current subsection) is advanced, the intervening bytes are filled with fill which should be an absolute expression. If the comma and fill are omitted, fill defaults to zero.
.p2align[wl]
abs-expr,
abs-expr,
abs-exprPad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the number of low-order zero bits the location counter must have after advancement. For example ‘.p2align 3’ advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed.
The second expression (also absolute) gives the fill value to be stored in the padding bytes. It (and the comma) may be omitted. If it is omitted, the padding bytes are normally zero. However, on most systems, if the section is marked as containing code and the fill value is omitted, the space is filled with no-op instructions.
The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by this alignment directive. If doing the alignment would require skipping more bytes than the specified maximum, then the alignment is not done at all. You can omit the fill value (the second argument) entirely by simply using two commas after the required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate.
The .p2alignw
and .p2alignl
directives are variants of the
.p2align
directive. The .p2alignw
directive treats the fill
pattern as a two byte word value. The .p2alignl
directives treats the
fill pattern as a four byte longword value. For example, .p2alignw
2,0x368d
will align to a multiple of 4. If it skips two bytes, they will be
filled in with the value 0x368d (the exact placement of the bytes depends upon
the endianness of the processor). If it skips 1 or 3 bytes, the fill value is
undefined.
.popsection
This is one of the ELF section stack manipulation directives. The others are
.section
(see Section), .subsection
(see SubSection),
.pushsection
(see PushSection), and .previous
(see Previous).
This directive replaces the current section (and subsection) with the top section (and subsection) on the section stack. This section is popped off the stack.
.previous
This is one of the ELF section stack manipulation directives. The others are
.section
(see Section), .subsection
(see SubSection),
.pushsection
(see PushSection), and .popsection
(see PopSection).
This directive swaps the current section (and subsection) with most recently
referenced section/subsection pair prior to this one. Multiple
.previous
directives in a row will flip between two sections (and their
subsections). For example:
.section A .subsection 1 .word 0x1234 .subsection 2 .word 0x5678 .previous .word 0x9abc
Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into subsection 2 of section A. Whilst:
.section A .subsection 1 # Now in section A subsection 1 .word 0x1234 .section B .subsection 0 # Now in section B subsection 0 .word 0x5678 .subsection 1 # Now in section B subsection 1 .word 0x9abc .previous # Now in section B subsection 0 .word 0xdef0
Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 0 of section B and 0x9abc into subsection 1 of section B.
In terms of the section stack, this directive swaps the current section with the top section on the section stack.
.print
stringas will print string on the standard output during assembly. You must put string in double quotes.
.protected
namesThis is one of the ELF visibility directives. The other two are
.hidden
(see Hidden) and .internal
(see Internal).
This directive overrides the named symbols default visibility (which is set by
their binding: local, global or weak). The directive sets the visibility to
protected
which means that any references to the symbols from within the
components that defines them must be resolved to the definition in that
component, even if a definition in another component would normally preempt
this.
.psize
lines ,
columnsUse this directive to declare the number of lines—and, optionally, the number of columns—to use for each page, when generating listings.
If you do not use .psize
, listings use a default line-count
of 60. You may omit the comma and columns specification; the
default width is 200 columns.
as generates formfeeds whenever the specified number of
lines is exceeded (or whenever you explicitly request one, using
.eject
).
If you specify lines as 0
, no formfeeds are generated save
those explicitly specified with .eject
.
.purgem
nameUndefine the macro name, so that later uses of the string will not be expanded. See Macro.
.pushsection
name [,
subsection] [, "
flags"[, @
type[,
arguments]]]
This is one of the ELF section stack manipulation directives. The others are
.section
(see Section), .subsection
(see SubSection),
.popsection
(see PopSection), and .previous
(see Previous).
This directive pushes the current section (and subsection) onto the
top of the section stack, and then replaces the current section and
subsection with name
and subsection
. The optional
flags
, type
and arguments
are treated the same
as in the .section
(see Section) directive.
.quad
bignums.quad
expects zero or more bignums, separated by commas. For
each bignum, it emits
an 8-byte integer. If the bignum won't fit in 8 bytes, it prints a
warning message; and just takes the lowest order 8 bytes of the bignum.
The term “quad” comes from contexts in which a “word” is two bytes;
hence quad-word for 8 bytes.
.reloc
offset,
reloc_name[,
expression]
Generate a relocation at offset of type reloc_name with value expression. If offset is a number, the relocation is generated in the current section. If offset is an expression that resolves to a symbol plus offset, the relocation is generated in the given symbol's section. expression, if present, must resolve to a symbol plus addend or to an absolute value, but note that not all targets support an addend. e.g. ELF REL targets such as i386 store an addend in the section contents rather than in the relocation. This low level interface does not support addends stored in the section.
.rept
countRepeat the sequence of lines between the .rept
directive and the next
.endr
directive count times.
For example, assembling
.rept 3 .long 0 .endr
is equivalent to assembling
.long 0 .long 0 .long 0
A count of zero is allowed, but nothing is generated. Negative counts are not allowed and if encountered will be treated as if they were zero.
.sbttl "
subheading"
Use subheading as the title (third line, immediately after the title line) when generating assembly listings.
This directive affects subsequent pages, as well as the current page if it appears within ten lines of the top of a page.
.scl
classSet the storage-class value for a symbol. This directive may only be
used inside a .def
/.endef
pair. Storage class may flag
whether a symbol is static or external, or it may record further
symbolic debugging information.
.section
nameUse the .section
directive to assemble the following code into a section
named name.
This directive is only supported for targets that actually support arbitrarily
named sections; on a.out
targets, for example, it is not accepted, even
with a standard a.out
section name.
For COFF targets, the .section
directive is used in one of the following
ways:
.section name[, "flags"] .section name[, subsection]
If the optional argument is quoted, it is taken as flags to use for the section. Each flag is a single character. The following flags are recognized:
b
n
w
d
e
r
x
s
a
y
0-9
If no flags are specified, the default flags depend upon the section name. If
the section name is not recognized, the default will be for the section to be
loaded and writable. Note the n
and w
flags remove attributes
from the section, rather than adding them, so if they are used on their own it
will be as if no flags had been specified at all.
If the optional argument to the .section
directive is not quoted, it is
taken as a subsection number (see Sub-Sections).
This is one of the ELF section stack manipulation directives. The others are
.subsection
(see SubSection), .pushsection
(see PushSection), .popsection
(see PopSection), and
.previous
(see Previous).
For ELF targets, the .section
directive is used like this:
.section name [, "flags"[, @type[,flag_specific_arguments]]]
If the ‘--sectname-subst’ command-line option is provided, the name
argument may contain a substitution sequence. Only %S
is supported
at the moment, and substitutes the current section name. For example:
.macro exception_code .section %S.exception [exception code here] .previous .endm .text [code] exception_code [...] .section .init [init code] exception_code [...]
The two exception_code
invocations above would create the
.text.exception
and .init.exception
sections respectively.
This is useful e.g. to discriminate between ancillary sections that are
tied to setup code to be discarded after use from ancillary sections that
need to stay resident without having to define multiple exception_code
macros just for that purpose.
The optional flags argument is a quoted string which may contain any combination of the following characters:
a
d
e
w
x
M
S
G
T
?
<number>
<target specific>
Note - once a section's flags have been set they cannot be changed. There are
a few exceptions to this rule however. Processor and application specific
flags can be added to an already defined section. The .interp
,
.strtab
and .symtab
sections can have the allocate flag
(a
) set after they are initially defined, and the .note-GNU-stack
section may have the executable (x
) flag added.
The optional type argument may contain one of the following constants:
@progbits
@nobits
@note
@init_array
@fini_array
@preinit_array
@<number>
@<target specific>
Many targets only support the first three section types. The type may be enclosed in double quotes if necessary.
Note on targets where the @
character is the start of a comment (eg
ARM) then another character is used instead. For example the ARM port uses the
%
character.
Note - some sections, eg .text
and .data
are considered to be
special and have fixed types. Any attempt to declare them with a different
type will generate an error from the assembler.
If flags contains the M
symbol then the type argument must
be specified as well as an extra argument—entsize—like this:
.section name , "flags"M, @type, entsize
Sections with the M
flag but not S
flag must contain fixed size
constants, each entsize octets long. Sections with both M
and
S
must contain zero terminated strings where each character is
entsize bytes long. The linker may remove duplicates within sections with
the same name, same entity size and same flags. entsize must be an
absolute expression. For sections with both M
and S
, a string
which is a suffix of a larger string is considered a duplicate. Thus
"def"
will be merged with "abcdef"
; A reference to the first
"def"
will be changed to a reference to "abcdef"+3
.
If flags contains the G
symbol then the type argument must
be present along with an additional field like this:
.section name , "flags"G, @type, GroupName[, linkage]
The GroupName field specifies the name of the section group to which this particular section belongs. The optional linkage field can contain:
comdat
.gnu.linkonce
Note: if both the M and G flags are present then the fields for the Merge flag should come first, like this:
.section name , "flags"MG, @type, entsize, GroupName[, linkage]
If flags contains the ?
symbol then it may not also contain the
G
symbol and the GroupName or linkage fields should not be
present. Instead, ?
says to consider the section that's current before
this directive. If that section used G
, then the new section will use
G
with those same GroupName and linkage fields implicitly.
If not, then the ?
symbol has no effect.
If no flags are specified, the default flags depend upon the section name. If the section name is not recognized, the default will be for the section to have none of the above flags: it will not be allocated in memory, nor writable, nor executable. The section will contain data.
For ELF targets, the assembler supports another type of .section
directive for compatibility with the Solaris assembler:
.section "name"[, flags...]
Note that the section name is quoted. There may be a sequence of comma separated flags:
#alloc
#write
#execinstr
#exclude
#tls
This directive replaces the current section and subsection. See the
contents of the gas testsuite directory gas/testsuite/gas/elf
for
some examples of how this directive and the other section stack directives
work.
.set
symbol,
expressionSet the value of symbol to expression. This changes symbol's value and type to conform to expression. If symbol was flagged as external, it remains flagged (see Symbol Attributes).
You may .set
a symbol many times in the same assembly provided that the
values given to the symbol are constants. Values that are based on expressions
involving other symbols are allowed, but some targets may restrict this to only
being done once per assembly. This is because those targets do not set the
addresses of symbols at assembly time, but rather delay the assignment until a
final link is performed. This allows the linker a chance to change the code in
the files, changing the location of, and the relative distance between, various
different symbols.
If you .set
a global symbol, the value stored in the object
file is the last value stored into it.
On Z80 set
is a real instruction, use
‘symbol defl expression’ instead.
.short
expressions.short
is normally the same as ‘.word’.
See .word
.
In some configurations, however, .short
and .word
generate
numbers of different lengths. See Machine Dependencies.
.single
flonumsThis directive assembles zero or more flonums, separated by commas. It
has the same effect as .float
.
The exact kind of floating point numbers emitted depends on how
as is configured. See Machine Dependencies.
.size
This directive is used to set the size associated with a symbol.
For COFF targets, the .size
directive is only permitted inside
.def
/.endef
pairs. It is used like this:
.size expression
For ELF targets, the .size
directive is used like this:
.size name , expression
This directive sets the size associated with a symbol name. The size in bytes is computed from expression which can make use of label arithmetic. This directive is typically used to set the size of function symbols.
.skip
size [,
fill]
This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero. This is the same as ‘.space’.
.sleb128
expressionssleb128 stands for “signed little endian base 128.” This is a
compact, variable length representation of numbers used by the DWARF
symbolic debugging format. See .uleb128
.
.space
size [,
fill]
This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero. This is the same as ‘.skip’.
Warning:.space
has a completely different meaning for HPPA targets; use.block
as a substitute. See HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001) for the meaning of the.space
directive. See HPPA Assembler Directives, for a summary.
.stabd, .stabn, .stabs
There are three directives that begin ‘.stab’. All emit symbols (see Symbols), for use by symbolic debuggers. The symbols are not entered in the as hash table: they cannot be referenced elsewhere in the source file. Up to five fields are required:
ld
and debuggers choke on silly bit patterns.
If a warning is detected while reading a .stabd
, .stabn
,
or .stabs
statement, the symbol has probably already been created;
you get a half-formed symbol in your object file. This is
compatible with earlier assemblers!
.stabd
type ,
other ,
descThe symbol's value is set to the location counter,
relocatably. When your program is linked, the value of this symbol
is the address of the location counter when the .stabd
was
assembled.
.stabn
type ,
other ,
desc ,
value""
.
.stabs
string ,
type ,
other ,
desc ,
value.string
"str", .string8
"str", .string16
"str", .string32
"str", .string64
"str"
Copy the characters in str to the object file. You may specify more than one string to copy, separated by commas. Unless otherwise specified for a particular machine, the assembler marks the end of each string with a 0 byte. You can use any of the escape sequences described in Strings.
The variants string16
, string32
and string64
differ from
the string
pseudo opcode in that each 8-bit character from str is
copied and expanded to 16, 32 or 64 bits respectively. The expanded characters
are stored in target endianness byte order.
Example:
.string32 "BYE" expands to: .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */
.struct
expressionSwitch to the absolute section, and set the section offset to expression, which must be an absolute expression. You might use this as follows:
.struct 0 field1: .struct field1 + 4 field2: .struct field2 + 4 field3:
This would define the symbol field1
to have the value 0, the symbol
field2
to have the value 4, and the symbol field3
to have the
value 8. Assembly would be left in the absolute section, and you would need to
use a .section
directive of some sort to change to some other section
before further assembly.
.subsection
nameThis is one of the ELF section stack manipulation directives. The others are
.section
(see Section), .pushsection
(see PushSection),
.popsection
(see PopSection), and .previous
(see Previous).
This directive replaces the current subsection with name
. The current
section is not changed. The replaced subsection is put onto the section stack
in place of the then current top of stack subsection.
.symver
Use the .symver
directive to bind symbols to specific version nodes
within a source file. This is only supported on ELF platforms, and is
typically used when assembling files to be linked into a shared library.
There are cases where it may make sense to use this in objects to be bound
into an application itself so as to override a versioned symbol from a
shared library.
For ELF targets, the .symver
directive can be used like this:
.symver name, name2@nodename
If the symbol name is defined within the file
being assembled, the .symver
directive effectively creates a symbol
alias with the name name2@nodename, and in fact the main reason that we
just don't try and create a regular alias is that the @ character isn't
permitted in symbol names. The name2 part of the name is the actual name
of the symbol by which it will be externally referenced. The name name
itself is merely a name of convenience that is used so that it is possible to
have definitions for multiple versions of a function within a single source
file, and so that the compiler can unambiguously know which version of a
function is being mentioned. The nodename portion of the alias should be
the name of a node specified in the version script supplied to the linker when
building a shared library. If you are attempting to override a versioned
symbol from a shared library, then nodename should correspond to the
nodename of the symbol you are trying to override.
If the symbol name is not defined within the file being assembled, all references to name will be changed to name2@nodename. If no reference to name is made, name2@nodename will be removed from the symbol table.
Another usage of the .symver
directive is:
.symver name, name2@@nodename
In this case, the symbol name must exist and be defined within the file being assembled. It is similar to name2@nodename. The difference is name2@@nodename will also be used to resolve references to name2 by the linker.
The third usage of the .symver
directive is:
.symver name, name2@@@nodename
When name is not defined within the file being assembled, it is treated as name2@nodename. When name is defined within the file being assembled, the symbol name, name, will be changed to name2@@nodename.
.tag
structnameThis directive is generated by compilers to include auxiliary debugging
information in the symbol table. It is only permitted inside
.def
/.endef
pairs. Tags are used to link structure
definitions in the symbol table with instances of those structures.
.text
subsectionTells as to assemble the following statements onto the end of the text subsection numbered subsection, which is an absolute expression. If subsection is omitted, subsection number zero is used.
.title "
heading"
Use heading as the title (second line, immediately after the source file name and pagenumber) when generating assembly listings.
This directive affects subsequent pages, as well as the current page if it appears within ten lines of the top of a page.
.type
This directive is used to set the type of a symbol.
For COFF targets, this directive is permitted only within
.def
/.endef
pairs. It is used like this:
.type int
This records the integer int as the type attribute of a symbol table entry.
For ELF targets, the .type
directive is used like this:
.type name , type description
This sets the type of symbol name to be either a function symbol or an object symbol. There are five different syntaxes supported for the type description field, in order to provide compatibility with various other assemblers.
Because some of the characters used in these syntaxes (such as ‘@’ and ‘#’) are comment characters for some architectures, some of the syntaxes below do not work on all architectures. The first variant will be accepted by the GNU assembler on all architectures so that variant should be used for maximum portability, if you do not need to assemble your code with other assemblers.
The syntaxes supported are:
.type <name> STT_<TYPE_IN_UPPER_CASE> .type <name>,#<type> .type <name>,@<type> .type <name>,%<type> .type <name>,"<type>"
The types supported are:
STT_FUNC
function
STT_GNU_IFUNC
gnu_indirect_function
STT_OBJECT
object
STT_TLS
tls_object
STT_COMMON
common
STT_NOTYPE
notype
gnu_unique_object
Changing between incompatible types other than from/to STT_NOTYPE will result in a diagnostic. An intermediate change to STT_NOTYPE will silence this.
Note: Some targets support extra types in addition to those listed above.
.uleb128
expressionsuleb128 stands for “unsigned little endian base 128.” This is a
compact, variable length representation of numbers used by the DWARF
symbolic debugging format. See .sleb128
.
.val
addrThis directive, permitted only within .def
/.endef
pairs,
records the address addr as the value attribute of a symbol table
entry.
.version "
string"
This directive creates a .note
section and places into it an ELF
formatted note of type NT_VERSION. The note's name is set to string
.
.vtable_entry
table,
offsetThis directive finds or creates a symbol table
and creates a
VTABLE_ENTRY
relocation for it with an addend of offset
.
.vtable_inherit
child,
parentThis directive finds the symbol child
and finds or creates the symbol
parent
and then creates a VTABLE_INHERIT
relocation for the
parent whose addend is the value of the child symbol. As a special case the
parent name of 0
is treated as referring to the *ABS*
section.
.warning "
string"
Similar to the directive .error
(see .error "
string"
), but just emits a warning.
.weak
namesThis directive sets the weak attribute on the comma separated list of symbol
names
. If the symbols do not already exist, they will be created.
On COFF targets other than PE, weak symbols are a GNU extension. This
directive sets the weak attribute on the comma separated list of symbol
names
. If the symbols do not already exist, they will be created.
On the PE target, weak symbols are supported natively as weak aliases. When a weak symbol is created that is not an alias, GAS creates an alternate symbol to hold the default value.
.weakref
alias,
targetThis directive creates an alias to the target symbol that enables the symbol to be referenced with weak-symbol semantics, but without actually making it weak. If direct references or definitions of the symbol are present, then the symbol will not be weak, but if all references to it are through weak references, the symbol will be marked as weak in the symbol table.
The effect is equivalent to moving all references to the alias to a separate assembly source file, renaming the alias to the symbol in it, declaring the symbol as weak there, and running a reloadable link to merge the object files resulting from the assembly of the new source file and the old source file that had the references to the alias removed.
The alias itself never makes to the symbol table, and is entirely handled within the assembler.
.word
expressionsThis directive expects zero or more expressions, of any section, separated by commas.
The size of the number emitted, and its byte order, depend on what target computer the assembly is for.
Warning: Special Treatment to support Compilers
Machines with a 32-bit address space, but that do less than 32-bit addressing, require the following special treatment. If the machine of interest to you does 32-bit addressing (or doesn't require it; see Machine Dependencies), you can ignore this issue.
In order to assemble compiler output into something that works,
as occasionally does strange things to ‘.word’ directives.
Directives of the form ‘.word sym1-sym2’ are often emitted by
compilers as part of jump tables. Therefore, when as assembles a
directive of the form ‘.word sym1-sym2’, and the difference between
sym1
and sym2
does not fit in 16 bits, as
creates a secondary jump table, immediately before the next label.
This secondary jump table is preceded by a short-jump to the
first byte after the secondary table. This short-jump prevents the flow
of control from accidentally falling into the new table. Inside the
table is a long-jump to sym2
. The original ‘.word’
contains sym1
minus the address of the long-jump to
sym2
.
If there were several occurrences of ‘.word sym1-sym2’ before the
secondary jump table, all of them are adjusted. If there was a
‘.word sym3-sym4’, that also did not fit in sixteen bits, a
long-jump to sym4
is included in the secondary jump table,
and the .word
directives are adjusted to contain sym3
minus the address of the long-jump to sym4
; and so on, for as many
entries in the original jump table as necessary.
.zero
sizeThis directive emits size 0-valued bytes. size must be an absolute expression. This directive is actually an alias for the ‘.skip’ directive so it can take an optional second argument of the value to store in the bytes instead of zero. Using ‘.zero’ in this way would be confusing however.
.2byte
expression [,
expression]*
This directive expects zero or more expressions, separated by commas. If there are no expressions then the directive does nothing. Otherwise each expression is evaluated in turn and placed in the next two bytes of the current output section, using the endian model of the target. If an expression will not fit in two bytes, a warning message is displayed and the least significant two bytes of the expression's value are used. If an expression cannot be evaluated at assembly time then relocations will be generated in order to compute the value at link time.
This directive does not apply any alignment before or after inserting the values. As a result of this, if relocations are generated, they may be different from those used for inserting values with a guaranteed alignment.
This directive is only available for ELF targets,
.4byte
expression [,
expression]*
Like the .2byte directive, except that it inserts unaligned, four byte long values into the output.
.8byte
expression [,
expression]*
Like the .2byte directive, except that it inserts unaligned, eight byte long bignum values into the output.
One day these directives won't work. They are included for compatibility with older assemblers.
as assembles source files written for a specific architecture into object files for that architecture. But not all object files are alike. Many architectures support incompatible variations. For instance, floating point arguments might be passed in floating point registers if the object file requires hardware floating point support—or floating point arguments might be passed in integer registers if the object file supports processors with no hardware floating point unit. Or, if two objects are built for different generations of the same architecture, the combination may require the newer generation at run-time.
This information is useful during and after linking. At link time, ld can warn about incompatible object files. After link time, tools like gdb can use it to process the linked file correctly.
Compatibility information is recorded as a series of object attributes. Each attribute has a vendor, tag, and value. The vendor is a string, and indicates who sets the meaning of the tag. The tag is an integer, and indicates what property the attribute describes. The value may be a string or an integer, and indicates how the property affects this object. Missing attributes are the same as attributes with a zero value or empty string value.
Object attributes were developed as part of the ABI for the ARM Architecture. The file format is documented in ELF for the ARM Architecture.
The .gnu_attribute
directive records an object attribute
with vendor ‘gnu’.
Except for ‘Tag_compatibility’, which has both an integer and a string for
its value, gnu attributes have a string value if the tag number is odd and
an integer value if the tag number is even. The second bit (tag &
2
is set for architecture-independent attributes and clear for
architecture-dependent ones.
These attributes are valid on all architectures.
If you want to define a new gnu object attribute, here are the places you will need to modify. New attributes should be discussed on the ‘binutils’ mailing list.
The machine instruction sets are (almost by definition) different on each machine where as runs. Floating point representations vary as well, and as often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform. Finally, some versions of as support special pseudo-instructions for branch optimization.
This chapter discusses most of these differences, though it does not include details on any machine's instruction set. For details on that subject, see the hardware manufacturer's manual.
The documentation here is primarily for the ELF object format.
as
also supports the ECOFF and EVAX formats, but
features specific to these formats are not yet documented.
-m
cpu.arch
directive.
The following processor names are recognized:
21064
,
21064a
,
21066
,
21068
,
21164
,
21164a
,
21164pc
,
21264
,
21264a
,
21264b
,
ev4
,
ev5
,
lca45
,
ev5
,
ev56
,
pca56
,
ev6
,
ev67
,
ev68
.
The special name all
may be used to allow the assembler to accept
instructions valid for any Alpha processor.
In order to support existing practice in OSF/1 with respect to .arch
,
and existing practice within MILO (the Linux ARC bootloader), the
numbered processor names (e.g. 21064) enable the processor-specific PALcode
instructions, while the “electro-vlasic” names (e.g. ev4
) do not.
-mdebug
-no-mdebug
.mdebug
encapsulation for
stabs directives and procedure descriptors. The default is to automatically
enable .mdebug
when the first stabs directive is seen.
-relax
-replace
-noreplace
-replace
is the default. See section 1.4.1 of the OpenVMS Linker
Utility Manual.
-g
-G
size.bss
,
while smaller symbols are placed in .sbss
.
-F
-32addr
The assembler syntax closely follow the Alpha Reference Manual; assembler directives and general syntax closely follow the OSF/1 and OpenVMS syntax, with a few differences for ELF.
‘#’ is the line comment character. Note that if ‘#’ is the first character on a line then it can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
‘;’ can be used instead of a newline to separate statements.
The 32 integer registers are referred to as ‘$n’ or ‘$rn’. In addition, registers 15, 28, 29, and 30 may be referred to by the symbols ‘$fp’, ‘$at’, ‘$gp’, and ‘$sp’ respectively.
The 32 floating-point registers are referred to as ‘$fn’.
Some of these relocations are available for ECOFF, but mostly only for ELF. They are modeled after the relocation format introduced in Digital Unix 4.0, but there are additions.
The format is ‘!tag’ or ‘!tag!number’ where tag is the name of the relocation. In some cases number is used to relate specific instructions.
The relocation is placed at the end of the instruction like so:
ldah $0,a($29) !gprelhigh lda $0,a($0) !gprellow ldq $1,b($29) !literal!100 ldl $2,0($1) !lituse_base!100
!literal
!literal!
Nldq
instruction to load the address of a symbol
from the GOT.
A sequence number N is optional, and if present is used to pair
lituse
relocations with this literal
relocation. The
lituse
relocations are used by the linker to optimize the code
based on the final location of the symbol.
Note that these optimizations are dependent on the data flow of the
program. Therefore, if any lituse
is paired with a
literal
relocation, then all uses of the register set by
the literal
instruction must also be marked with lituse
relocations. This is because the original literal
instruction
may be deleted or transformed into another instruction.
Also note that there may be a one-to-many relationship between
literal
and lituse
, but not a many-to-one. That is, if
there are two code paths that load up the same address and feed the
value to a single use, then the use may not use a lituse
relocation.
!lituse_base!
Nldl
) to indicate
that the literal is used for an address load. The offset field of the
instruction must be zero. During relaxation, the code may be altered
to use a gp-relative load.
!lituse_jsr!
Njsr
) to
indicate that the literal is used for a call. During relaxation, the
code may be altered to use a direct branch (e.g. bsr
).
!lituse_jsrdirect!
Nlituse_jsr
, but also that this call cannot be vectored
through a PLT entry. This is useful for functions with special calling
conventions which do not allow the normal call-clobbered registers to be
clobbered.
!lituse_bytoff!
Nextbl
) to indicate
that only the low 3 bits of the address are relevant. During relaxation,
the code may be altered to use an immediate instead of a register shift.
!lituse_addr!
Nldq
instruction may not be
altered or deleted. This is useful in conjunction with lituse_jsr
to test whether a weak symbol is defined.
ldq $27,foo($29) !literal!1 beq $27,is_undef !lituse_addr!1 jsr $26,($27),foo !lituse_jsr!1
!lituse_tlsgd!
N__tls_get_addr
used to compute the
address of the thread-local storage variable whose descriptor was
loaded with !tlsgd!
N.
!lituse_tlsldm!
N__tls_get_addr
used to compute the
address of the base of the thread-local storage block for the current
module. The descriptor for the module must have been loaded with
!tlsldm!
N.
!gpdisp!
Nldah
and lda
to load the GP from the current
address, a-la the ldgp
macro. The source register for the
ldah
instruction must contain the address of the ldah
instruction. There must be exactly one lda
instruction paired
with the ldah
instruction, though it may appear anywhere in
the instruction stream. The immediate operands must be zero.
bsr $26,foo ldah $29,0($26) !gpdisp!1 lda $29,0($29) !gpdisp!1
!gprelhigh
ldah
instruction to add the high 16 bits of a
32-bit displacement from the GP.
!gprellow
!gprel
!samegp
$27
or perform a standard GP load in the first two instructions via the
.prologue
directive.
!tlsgd
!tlsgd!
Nlda
instruction to load the address of a TLS
descriptor for a symbol in the GOT.
The sequence number N is optional, and if present it used to
pair the descriptor load with both the literal
loading the
address of the __tls_get_addr
function and the lituse_tlsgd
marking the call to that function.
For proper relaxation, both the tlsgd
, literal
and
lituse
relocations must be in the same extended basic block.
That is, the relocation with the lowest address must be executed
first at runtime.
!tlsldm
!tlsldm!
Nlda
instruction to load the address of a TLS
descriptor for the current module in the GOT.
Similar in other respects to tlsgd
.
!gotdtprel
ldq
instruction to load the offset of the TLS
symbol within its module's thread-local storage block. Also known
as the dynamic thread pointer offset or dtp-relative offset.
!dtprelhi
!dtprello
!dtprel
gprel
relocations except they compute dtp-relative offsets.
!gottprel
ldq
instruction to load the offset of the TLS
symbol from the thread pointer. Also known as the tp-relative offset.
!tprelhi
!tprello
!tprel
gprel
relocations except they compute tp-relative offsets.
The Alpha family uses both ieee and VAX floating-point numbers.
as for the Alpha supports many additional directives for compatibility with the native assembler. This section describes them only briefly.
These are the additional directives in as
for the Alpha:
.arch
cpu.ent
function[,
n]
.mdebug
information, this will create a procedure descriptor for
the function. In ELF, it will mark the symbol as a function a-la the
generic .type
directive.
.end
function.size
directive.
.mask
mask,
offset$26
) is saved first.
This and the other directives that describe the stack frame are
currently only used when generating .mdebug
information. They
may in the future be used to generate DWARF2 .debug_frame
unwind
information for hand written assembly.
.fmask
mask,
offset.mask
.
.frame
framereg,
frameoffset,
retreg[,
argoffset]
$fp
or $sp
. The
frame pointer is frameoffset bytes below the CFA. The return
address is initially located in retreg until it is saved as
indicated in .mask
. For compatibility with OSF/1 an optional
argoffset parameter is accepted and ignored. It is believed to
indicate the offset from the CFA to the saved argument registers.
.prologue
n$27
. 0 indicates that $27
is not used; 1
indicates that the first two instructions of the function use $27
to perform a load of the GP register; 2 indicates that $27
is
used in some non-standard way and so the linker cannot elide the load of
the procedure vector during relaxation.
.usepv
function,
which$27
register, similar to
.prologue
, but without the other semantics of needing to
be inside an open .ent
/.end
block.
The which argument should be either no
, indicating that
$27
is not used, or std
, indicating that the first two
instructions of the function perform a GP load.
One might use this directive instead of .prologue
if you are
also using dwarf2 CFI directives.
.gprel32
expression.t_floating
expression.s_floating
expression.f_floating
expression.g_floating
expression.d_floating
expression.set
featureat
$at
or $28
) register. Some macros may not be
expanded without this and will generate an error message if noat
is in effect. When at
is in effect, a warning will be generated
if $at
is used by the programmer.
macro
br label
vs br $31,label
are
considered alternate forms and not macros.
move
reorder
volatile
The following directives are recognized for compatibility with the OSF/1 assembler but are ignored.
.proc .aproc .reguse .livereg .option .aent .ugen .eflag .alias .noalias
For detailed information on the Alpha machine instruction set, see the Alpha Architecture Handbook.
The following options control the type of CPU for which code is assembled, and generic constraints on the code generated:
-mcpu=
cpuarc600
-mA6
, -mARC600
.
arc600_norm
arc600_mul64
arc600_mul32x16
arc601
-mARC601
.
arc601_norm
arc601_mul64
arc601_mul32x16
arc700
-mA7
, -mARC700
.
arcem
-mEM
em
em4
em4_dmips
em4_fpus
em4_fpuda
quarkse_em
archs
-mHS
, -mav2hs
.
hs
hs34
hs38
hs38_linux
nps400
Note: the .cpu
directive (see ARC Directives) can
to be used to select a core variant from within assembly code.
-EB
-EL
-mcode-density
-mrelax
-mnps400
-mspfp
-mdpfp
-mfpuda
%
%r0
is equivalent to r0
in the assembly code.
#
Note: if a line starts with a ‘#’ character then it can
also be a logical line number directive (see Comments) or a
preprocessor control command (see Preprocessing).
@
mov r0, @r0
moves the address of symbol r0
into register r0
.
`
-
The ARC assembler uses the following register names for its core registers:
r0-r31
r26
through r31
have special functions, and are usually referred to by those synonyms.
gp
r26
.
fp
r27
.
sp
r28
.
ilink1
r29
. Not supported for ARCv2.
ilink
r29
.
Not supported for ARC 600 and ARC 700.
ilink2
r30
. Not supported for ARC v2.
blink
r31
.
r32-r59
lp_count
pcl
In addition the ARC processor has a large number of auxiliary registers. The precise set depends on the extensions being supported, but the following baseline set are always defined:
identity
pc
status32
bta
ecr
int_vector_base
status32_p0
aux_user_sp
eret
erbta
erstatus
bcr_ver
bta_link_build
vecbase_ac_build
rf_build
dccm_build
Additional auxiliary register names are defined according to the processor architecture version and extensions selected by the options.
The ARC version of as
supports the following additional
machine directives:
.lcomm
symbol,
length[,
alignment]
ld
. The optional third parameter, alignment,
specifies the desired alignment of the symbol in the bss section,
specified as a byte boundary (for example, an alignment of 16 means
that the least significant 4 bits of the address should be zero). The
alignment must be an absolute expression, and it must be a power of
two. If no alignment is specified, as will set the alignment to the
largest power of two less than or equal to the size of the symbol, up
to a maximum of 16.
.lcommon
symbol,
length[,
alignment]
lcomm
directive.
.cpu
cpu.cpu
directive must be followed by the desired core
version. Permitted values for CPU are:
ARC600
arc600_norm
arc600_mul64
arc600_mul32x16
arc601
arc601_norm
arc601_mul64
arc601_mul32x16
ARC700
NPS400
EM
arcem
em4
em4_dmips
em4_fpus
em4_fpuda
quarkse_em
HS
archs
hs
hs34
hs38
hs38_linux
Note: the .cpu
directive overrides the command-line option
-mcpu=
cpu; a warning is emitted when the version is not
consistent between the two.
.extAuxRegister
name,
addr,
moder
w
r|w
For example:
.extAuxRegister mulhi, 0x12, w
specifies a write only extension auxiliary register, mulhi at
address 0x12.
.extCondCode
suffix,
valFor example:
.extCondCode is_busy,0x14 add.is_busy r1,r2,r3
will only execute the add
instruction if the condition code
value is 0x14.
.extCoreRegister
name,
regnum,
mode,
shortcutr
w
r|w
The final parameter, shortcut indicates whether the register has a short cut in the pipeline. The valid values are:
can_shortcut
cannot_shortcut
For example:
.extCoreRegister mlo, 57, r , can_shortcut
defines a read only extension core register, mlo
, which is
register 57, and can short cut the pipeline.
.extInstruction
name,
opcode,
subopcode,
suffixclass,
syntaxclassThe first argument, name, gives the name of the instruction.
The second argument, opcode, is the opcode to be used (bits 31:27 in the encoding).
The third argument, subopcode, is the sub-opcode to be used, but the correct value also depends on the fifth argument, syntaxclass
The fourth argument, suffixclass, determines the kinds of suffixes to be allowed. Valid values are:
SUFFIX_NONE
SUFFIX_COND
SUFFIX_FLAG
SUFFIX_COND|SUFFIX_FLAG
The fifth and final argument, syntaxclass, determines the syntax class for the instruction. It can have the following values:
SYNTAX_2OP
SYNTAX_3OP
SYNTAX_1OP
SYNTAX_NOP
The syntax class may be followed by ‘|’ and one of the following modifiers.
OP1_MUST_BE_IMM
SYNTAX_3OP
, specifying that the first
operand of a three-operand instruction must be an immediate (i.e., the
result is discarded). This is usually used to set the flags using
specific instructions and not retain results.
OP1_IMM_IMPLIED
SYNTAX_20P
, specifying that there is an
implied immediate destination operand which does not appear in the
syntax.
For example, if the source code contains an instruction like:
inst r1,r2
the first argument is an implied immediate (that is, the result is discarded). This is the same as though the source code were: inst 0,r1,r2.
For example, defining a 64-bit multiplier with immediate operands:
.extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, SYNTAX_3OP|OP1_MUST_BE_IMM
which specifies an extension instruction named mp64
with 3
operands. It sets the flags and can be used with a condition code,
for which the first operand is an immediate, i.e. equivalent to
discarding the result of the operation.
A two operands instruction variant would be:
.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
which describes a two operand instruction with an implicit first immediate operand. The result of this operation would be discarded.
.arc_attribute
tag,
valueThe tag is either an attribute number, or one of the following:
Tag_ARC_PCS_config
, Tag_ARC_CPU_base
,
Tag_ARC_CPU_variation
, Tag_ARC_CPU_name
,
Tag_ARC_ABI_rf16
, Tag_ARC_ABI_osver
, Tag_ARC_ABI_sda
,
Tag_ARC_ABI_pic
, Tag_ARC_ABI_tls
, Tag_ARC_ABI_enumsize
,
Tag_ARC_ABI_exceptions
, Tag_ARC_ABI_double_size
,
Tag_ARC_ISA_config
, Tag_ARC_ISA_apex
,
Tag_ARC_ISA_mpy_option
The value is either a number
, "string"
, or
number, "string"
depending on the tag.
The following additional assembler modifiers have been added for position-independent code. These modifiers are available only with the ARC 700 and above processors and generate relocation entries, which are interpreted by the linker as follows:
@pcl(
symbol)
@gotpc(
symbol)
@gotoff(
symbol)
@plt(
symbol)
@sda(
symbol)
The following assembler symbols will prove useful when developing position-independent code. These symbols are available only with the ARC 700 and above processors.
__GLOBAL_OFFSET_TABLE__
__DYNAMIC__
Base__GLOBAL_OFFSET_TABLE__
. It can be used only with
@gotpc
modifiers.
For information on the ARC instruction set, see ARC Programmers Reference Manual, available where you download the processor IP library.
-mcpu=
processor[+
extension...]
arm1
,
arm2
,
arm250
,
arm3
,
arm6
,
arm60
,
arm600
,
arm610
,
arm620
,
arm7
,
arm7m
,
arm7d
,
arm7dm
,
arm7di
,
arm7dmi
,
arm70
,
arm700
,
arm700i
,
arm710
,
arm710t
,
arm720
,
arm720t
,
arm740t
,
arm710c
,
arm7100
,
arm7500
,
arm7500fe
,
arm7t
,
arm7tdmi
,
arm7tdmi-s
,
arm8
,
arm810
,
strongarm
,
strongarm1
,
strongarm110
,
strongarm1100
,
strongarm1110
,
arm9
,
arm920
,
arm920t
,
arm922t
,
arm940t
,
arm9tdmi
,
fa526
(Faraday FA526 processor),
fa626
(Faraday FA626 processor),
arm9e
,
arm926e
,
arm926ej-s
,
arm946e-r0
,
arm946e
,
arm946e-s
,
arm966e-r0
,
arm966e
,
arm966e-s
,
arm968e-s
,
arm10t
,
arm10tdmi
,
arm10e
,
arm1020
,
arm1020t
,
arm1020e
,
arm1022e
,
arm1026ej-s
,
fa606te
(Faraday FA606TE processor),
fa616te
(Faraday FA616TE processor),
fa626te
(Faraday FA626TE processor),
fmp626
(Faraday FMP626 processor),
fa726te
(Faraday FA726TE processor),
arm1136j-s
,
arm1136jf-s
,
arm1156t2-s
,
arm1156t2f-s
,
arm1176jz-s
,
arm1176jzf-s
,
mpcore
,
mpcorenovfp
,
cortex-a5
,
cortex-a7
,
cortex-a8
,
cortex-a9
,
cortex-a15
,
cortex-a17
,
cortex-a32
,
cortex-a35
,
cortex-a53
,
cortex-a55
,
cortex-a57
,
cortex-a72
,
cortex-a73
,
cortex-a75
,
cortex-a76
,
cortex-a76ae
,
cortex-a77
,
ares
,
cortex-r4
,
cortex-r4f
,
cortex-r5
,
cortex-r7
,
cortex-r8
,
cortex-r52
,
cortex-m35p
,
cortex-m33
,
cortex-m23
,
cortex-m7
,
cortex-m4
,
cortex-m3
,
cortex-m1
,
cortex-m0
,
cortex-m0plus
,
exynos-m1
,
marvell-pj4
,
marvell-whitney
,
neoverse-n1
,
xgene1
,
xgene2
,
ep9312
(ARM920 with Cirrus Maverick coprocessor),
i80200
(Intel XScale processor)
iwmmxt
(Intel XScale processor with Wireless MMX technology coprocessor)
and
xscale
.
The special name all
may be used to allow the
assembler to accept instructions valid for any ARM processor.
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, -mcpu=arm920+maverick
is equivalent to specifying -mcpu=ep9312
.
Multiple extensions may be specified, separated by a +
. The
extensions should be specified in ascending alphabetical order.
Some extensions may be restricted to particular architectures; this is documented in the list of extensions below.
Extension mnemonics may also be removed from those the assembler accepts.
This is done be prepending no
to the option that adds the extension.
Extensions that are removed should be listed after all extensions which have
been added, again in ascending alphabetical order. For example,
-mcpu=ep9312+nomaverick
is equivalent to specifying -mcpu=arm920
.
The following extensions are currently supported:
bf16
(BFloat16 extensions for v8.6-A architecture),
i8mm
(Int8 Matrix Multiply extensions for v8.6-A architecture),
crc
crypto
(Cryptography Extensions for v8-A architecture, implies fp+simd
),
dotprod
(Dot Product Extensions for v8.2-A architecture, implies fp+simd
),
fp
(Floating Point Extensions for v8-A architecture),
fp16
(FP16 Extensions for v8.2-A architecture, implies fp
),
fp16fml
(FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies fp16
),
idiv
(Integer Divide Extensions for v7-A and v7-R architectures),
iwmmxt
,
iwmmxt2
,
xscale
,
maverick
,
mp
(Multiprocessing Extensions for v7-A and v7-R
architectures),
os
(Operating System for v6M architecture),
predres
(Execution and Data Prediction Restriction Instruction for
v8-A architectures, added by default from v8.5-A),
sb
(Speculation Barrier Instruction for v8-A architectures, added by
default from v8.5-A),
sec
(Security Extensions for v6K and v7-A architectures),
simd
(Advanced SIMD Extensions for v8-A architecture, implies fp
),
virt
(Virtualization Extensions for v7-A architecture, implies
idiv
),
pan
(Privileged Access Never Extensions for v8-A architecture),
ras
(Reliability, Availability and Serviceability extensions
for v8-A architecture),
rdma
(ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
simd
)
and
xscale
.
-march=
architecture[+
extension...]
armv1
,
armv2
,
armv2a
,
armv2s
,
armv3
,
armv3m
,
armv4
,
armv4xm
,
armv4t
,
armv4txm
,
armv5
,
armv5t
,
armv5txm
,
armv5te
,
armv5texp
,
armv6
,
armv6j
,
armv6k
,
armv6z
,
armv6kz
,
armv6-m
,
armv6s-m
,
armv7
,
armv7-a
,
armv7ve
,
armv7-r
,
armv7-m
,
armv7e-m
,
armv8-a
,
armv8.1-a
,
armv8.2-a
,
armv8.3-a
,
armv8-r
,
armv8.4-a
,
armv8.5-a
,
armv8-m.base
,
armv8-m.main
,
armv8.1-m.main
,
armv8.6-a
,
iwmmxt
,
iwmmxt2
and
xscale
.
If both -mcpu
and
-march
are specified, the assembler will use
the setting for -mcpu
.
The architecture option can be extended with a set extension options. These
extensions are context sensitive, i.e. the same extension may mean different
things when used with different architectures. When used together with a
-mfpu
option, the union of both feature enablement is taken.
See their availability and meaning below:
For armv5te
, armv5texp
, armv5tej
, armv6
, armv6j
, armv6k
, armv6z
, armv6kz
, armv6zk
, armv6t2
, armv6kt2
and armv6zt2
:
+fp
: Enables VFPv2 instructions.
+nofp
: Disables all FPU instrunctions.
For armv7
:
+fp
: Enables VFPv3 instructions with 16 double-word registers.
+nofp
: Disables all FPU instructions.
For armv7-a
:
+fp
: Enables VFPv3 instructions with 16 double-word registers.
+vfpv3-d16
: Alias for +fp
.
+vfpv3
: Enables VFPv3 instructions with 32 double-word registers.
+vfpv3-d16-fp16
: Enables VFPv3 with half precision floating-point
conversion instructions and 16 double-word registers.
+vfpv3-fp16
: Enables VFPv3 with half precision floating-point conversion
instructions and 32 double-word registers.
+vfpv4-d16
: Enables VFPv4 instructions with 16 double-word registers.
+vfpv4
: Enables VFPv4 instructions with 32 double-word registers.
+simd
: Enables VFPv3 and NEONv1 instructions with 32 double-word
registers.
+neon
: Alias for +simd
.
+neon-vfpv3
: Alias for +simd
.
+neon-fp16
: Enables VFPv3, half precision floating-point conversion and
NEONv1 instructions with 32 double-word registers.
+neon-vfpv4
: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
double-word registers.
+mp
: Enables Multiprocessing Extensions.
+sec
: Enables Security Extensions.
+nofp
: Disables all FPU and NEON instructions.
+nosimd
: Disables all NEON instructions.
For armv7ve
:
+fp
: Enables VFPv4 instructions with 16 double-word registers.
+vfpv4-d16
: Alias for +fp
.
+vfpv3-d16
: Enables VFPv3 instructions with 16 double-word registers.
+vfpv3
: Enables VFPv3 instructions with 32 double-word registers.
+vfpv3-d16-fp16
: Enables VFPv3 with half precision floating-point
conversion instructions and 16 double-word registers.
+vfpv3-fp16
: Enables VFPv3 with half precision floating-point conversion
instructions and 32 double-word registers.
+vfpv4
: Enables VFPv4 instructions with 32 double-word registers.
+simd
: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
double-word registers.
+neon-vfpv4
: Alias for +simd
.
+neon
: Enables VFPv3 and NEONv1 instructions with 32 double-word
registers.
+neon-vfpv3
: Alias for +neon
.
+neon-fp16
: Enables VFPv3, half precision floating-point conversion and
NEONv1 instructions with 32 double-word registers.
double-word registers.
+nofp
: Disables all FPU and NEON instructions.
+nosimd
: Disables all NEON instructions.
For armv7-r
:
+fp.sp
: Enables single-precision only VFPv3 instructions with 16
double-word registers.
+vfpv3xd
: Alias for +fp.sp
.
+fp
: Enables VFPv3 instructions with 16 double-word registers.
+vfpv3-d16
: Alias for +fp
.
+vfpv3xd-fp16
: Enables single-precision only VFPv3 and half
floating-point conversion instructions with 16 double-word registers.
+vfpv3-d16-fp16
: Enables VFPv3 and half precision floating-point
conversion instructions with 16 double-word registers.
+idiv
: Enables integer division instructions in ARM mode.
+nofp
: Disables all FPU instructions.
For armv7e-m
:
+fp
: Enables single-precision only VFPv4 instructions with 16
double-word registers.
+vfpvf4-sp-d16
: Alias for +fp
.
+fpv5
: Enables single-precision only VFPv5 instructions with 16
double-word registers.
+fp.dp
: Enables VFPv5 instructions with 16 double-word registers.
+fpv5-d16"
: Alias for +fp.dp
.
+nofp
: Disables all FPU instructions.
For armv8-m.main
:
+dsp
: Enables DSP Extension.
+fp
: Enables single-precision only VFPv5 instructions with 16
double-word registers.
+fp.dp
: Enables VFPv5 instructions with 16 double-word registers.
+nofp
: Disables all FPU instructions.
+nodsp
: Disables DSP Extension.
For armv8.1-m.main
:
+dsp
: Enables DSP Extension.
+fp
: Enables single and half precision scalar Floating Point Extensions
for Armv8.1-M Mainline with 16 double-word registers.
+fp.dp
: Enables double precision scalar Floating Point Extensions for
Armv8.1-M Mainline, implies +fp
.
+mve
: Enables integer only M-profile Vector Extension for
Armv8.1-M Mainline, implies +dsp
.
+mve.fp
: Enables Floating Point M-profile Vector Extension for
Armv8.1-M Mainline, implies +mve
and +fp
.
+nofp
: Disables all FPU instructions.
+nodsp
: Disables DSP Extension.
+nomve
: Disables all M-profile Vector Extensions.
For armv8-a
:
+crc
: Enables CRC32 Extension.
+simd
: Enables VFP and NEON for Armv8-A.
+crypto
: Enables Cryptography Extensions for Armv8-A, implies
+simd
.
+sb
: Enables Speculation Barrier Instruction for Armv8-A.
+predres
: Enables Execution and Data Prediction Restriction Instruction
for Armv8-A.
+nofp
: Disables all FPU, NEON and Cryptography Extensions.
+nocrypto
: Disables Cryptography Extensions.
For armv8.1-a
:
+simd
: Enables VFP and NEON for Armv8.1-A.
+crypto
: Enables Cryptography Extensions for Armv8-A, implies
+simd
.
+sb
: Enables Speculation Barrier Instruction for Armv8-A.
+predres
: Enables Execution and Data Prediction Restriction Instruction
for Armv8-A.
+nofp
: Disables all FPU, NEON and Cryptography Extensions.
+nocrypto
: Disables Cryptography Extensions.
For armv8.2-a
and armv8.3-a
:
+simd
: Enables VFP and NEON for Armv8.1-A.
+fp16
: Enables FP16 Extension for Armv8.2-A, implies +simd
.
+fp16fml
: Enables FP16 Floating Point Multiplication Variant Extensions
for Armv8.2-A, implies +fp16
.
+crypto
: Enables Cryptography Extensions for Armv8-A, implies
+simd
.
+dotprod
: Enables Dot Product Extensions for Armv8.2-A, implies
+simd
.
+sb
: Enables Speculation Barrier Instruction for Armv8-A.
+predres
: Enables Execution and Data Prediction Restriction Instruction
for Armv8-A.
+nofp
: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+nocrypto
: Disables Cryptography Extensions.
For armv8.4-a
:
+simd
: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
Armv8.2-A.
+fp16
: Enables FP16 Floating Point and Floating Point Multiplication
Variant Extensions for Armv8.2-A, implies +simd
.
+crypto
: Enables Cryptography Extensions for Armv8-A, implies
+simd
.
+sb
: Enables Speculation Barrier Instruction for Armv8-A.
+predres
: Enables Execution and Data Prediction Restriction Instruction
for Armv8-A.
+nofp
: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+nocryptp
: Disables Cryptography Extensions.
For armv8.5-a
:
+simd
: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
Armv8.2-A.
+fp16
: Enables FP16 Floating Point and Floating Point Multiplication
Variant Extensions for Armv8.2-A, implies +simd
.
+crypto
: Enables Cryptography Extensions for Armv8-A, implies
+simd
.
+nofp
: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+nocryptp
: Disables Cryptography Extensions.
-mfpu=
floating-point-formatsoftfpa
,
fpe
,
fpe2
,
fpe3
,
fpa
,
fpa10
,
fpa11
,
arm7500fe
,
softvfp
,
softvfp+vfp
,
vfp
,
vfp10
,
vfp10-r0
,
vfp9
,
vfpxd
,
vfpv2
,
vfpv3
,
vfpv3-fp16
,
vfpv3-d16
,
vfpv3-d16-fp16
,
vfpv3xd
,
vfpv3xd-d16
,
vfpv4
,
vfpv4-d16
,
fpv4-sp-d16
,
fpv5-sp-d16
,
fpv5-d16
,
fp-armv8
,
arm1020t
,
arm1020e
,
arm1136jf-s
,
maverick
,
neon
,
neon-vfpv3
,
neon-fp16
,
neon-vfpv4
,
neon-fp-armv8
,
crypto-neon-fp-armv8
,
neon-fp-armv8.1
and
crypto-neon-fp-armv8.1
.
In addition to determining which instructions are assembled, this option
also affects the way in which the .double
assembler directive behaves
when assembling little-endian code.
The default is dependent on the processor selected. For Architecture 5 or later, the default is to assemble for VFP instructions; for earlier architectures the default is to assemble for FPA instructions.
-mfp16-format=
format.float16
directive.
The following format options are recognized:
ieee
,
alternative
.
If ieee
is specified then the IEEE 754-2008 half-precision floating
point format is used, if alternative
is specified then the Arm
alternative half-precision format is used. If this option is set on the
command line then the format is fixed and cannot be changed with
the float16_format
directive. If this value is not set then
the IEEE 754-2008 format is used until the format is explicitly set with
the float16_format
directive.
-mthumb
.code 16
directive.
-mthumb-interwork
ADR
and ADRL
pseudo opcodes.
-mimplicit-it=never
-mimplicit-it=always
-mimplicit-it=arm
-mimplicit-it=thumb
-mimplicit-it
option controls the behavior of the assembler when
conditional instructions are not enclosed in IT blocks.
There are four possible behaviors.
If never
is specified, such constructs cause a warning in ARM
code and an error in Thumb-2 code.
If always
is specified, such constructs are accepted in both
ARM and Thumb-2 code, where the IT instruction is added implicitly.
If arm
is specified, such constructs are accepted in ARM code
and cause an error in Thumb-2 code.
If thumb
is specified, such constructs cause a warning in ARM
code and are accepted in Thumb-2 code. If you omit this option, the
behavior is equivalent to -mimplicit-it=arm
.
-mapcs-26
-mapcs-32
-matpcs
-mapcs-float
-mapcs-reentrant
-mfloat-abi=
abisoft
,
softfp
and
hard
.
-meabi=
vergnu
,
4
and
5
.
-EB
Note: If a program is being built for a system with big-endian data and little-endian instructions then it should be assembled with the -EB option, (all of it, code and data) and then linked with the --be8 option. This will reverse the endianness of the instructions back to little-endian, but leave the data as big-endian.
-EL
-k
--fix-v4bx
BX
instructions in ARMv4 code. This is intended for use with
the linker option of the same name.
-mwarn-deprecated
-mno-warn-deprecated
-mccs
-mwarn-syms
-mno-warn-syms
Two slightly different syntaxes are support for ARM and THUMB
instructions. The default, divided
, uses the old style where
ARM and THUMB instructions had their own, separate syntaxes. The new,
unified
syntax, which can be selected via the .syntax
directive, and has the following main features:
#
prefix.
IT
instruction may appear, and if it does it is validated
against subsequent conditional affixes. In ARM mode it does not
generate machine code, in THUMB mode it does.
IT
instruction.
divided
syntax).
.N
and .W
suffixes are recognized and honored.
s
affix.
The presence of a ‘@’ anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘;’ character can be used instead of a newline to separate statements.
Either ‘#’ or ‘$’ can be used to indicate immediate operands.
*TODO* Explain about /data modifier on symbols.
*TODO* Explain about ARM register naming, and the predefined names.
Specific data relocations can be generated by putting the relocation name in parentheses after the symbol name. For example:
.word foo(TARGET1)
This will generate an ‘R_ARM_TARGET1’ relocation against the symbol
foo.
The following relocations are supported:
GOT
,
GOTOFF
,
TARGET1
,
TARGET2
,
SBREL
,
TLSGD
,
TLSLDM
,
TLSLDO
,
TLSDESC
,
TLSCALL
,
GOTTPOFF
,
GOT_PREL
and
TPOFF
.
For compatibility with older toolchains the assembler also accepts
(PLT)
after branch targets. On legacy targets this will
generate the deprecated ‘R_ARM_PLT32’ relocation. On EABI
targets it will encode either the ‘R_ARM_CALL’ or
‘R_ARM_JUMP24’ relocation, as appropriate.
Relocations for ‘MOVW’ and ‘MOVT’ instructions can be generated by prefixing the value with ‘#:lower16:’ and ‘#:upper16’ respectively. For example to load the 32-bit address of foo into r0:
MOVW r0, #:lower16:foo MOVT r0, #:upper16:foo
Relocations ‘R_ARM_THM_ALU_ABS_G0_NC’, ‘R_ARM_THM_ALU_ABS_G1_NC’, ‘R_ARM_THM_ALU_ABS_G2_NC’ and ‘R_ARM_THM_ALU_ABS_G3_NC’ can be generated by prefixing the value with ‘#:lower0_7:#’, ‘#:lower8_15:#’, ‘#:upper0_7:#’ and ‘#:upper8_15:#’ respectively. For example to load the 32-bit address of foo into r0:
MOVS r0, #:upper8_15:#foo LSLS r0, r0, #8 ADDS r0, #:upper0_7:#foo LSLS r0, r0, #8 ADDS r0, #:lower8_15:#foo LSLS r0, r0, #8 ADDS r0, #:lower0_7:#foo
Some NEON load/store instructions allow an optional address alignment qualifier. The ARM documentation specifies that this is indicated by ‘@ align’. However GAS already interprets the ‘@’ character as a "line comment" start, so ‘: align’ is used instead. For example:
vld1.8 {q0}, [r0, :128]
The ARM family uses ieee floating-point numbers.
.align
expression [,
expression]
.arch
nameSpecifying .arch
clears any previously selected architecture
extensions.
.arch_extension
name.arch_extension
may be used multiple times to add or remove extensions
incrementally to the architecture being compiled for.
.arm
.bss
.bss
section.
.cantunwind
.code [16|32]
.cpu
nameSpecifying .cpu
clears any previously selected architecture
extensions.
.dn
register name [
.type] [[
index]]
.qn
register name [
.type] [[
index]]
dn
and qn
directives are used to create typed
and/or indexed register aliases for use in Advanced SIMD Extension
(Neon) instructions. The former should be used to create aliases
of double-precision registers, and the latter to create aliases of
quad-precision registers.
If these directives are used to create typed aliases, those aliases can be used in Neon instructions instead of writing types after the mnemonic or after each operand. For example:
x .dn d2.f32 y .dn d3.f32 z .dn d4.f32[1] vmul x,y,z
This is equivalent to writing the following:
vmul.f32 d2,d3,d4[1]
Aliases created using dn
or qn
can be destroyed using
unreq
.
.eabi_attribute
tag,
valueThe tag is either an attribute number, or one of the following:
Tag_CPU_raw_name
, Tag_CPU_name
, Tag_CPU_arch
,
Tag_CPU_arch_profile
, Tag_ARM_ISA_use
,
Tag_THUMB_ISA_use
, Tag_FP_arch
, Tag_WMMX_arch
,
Tag_Advanced_SIMD_arch
, Tag_MVE_arch
, Tag_PCS_config
,
Tag_ABI_PCS_R9_use
, Tag_ABI_PCS_RW_data
,
Tag_ABI_PCS_RO_data
, Tag_ABI_PCS_GOT_use
,
Tag_ABI_PCS_wchar_t
, Tag_ABI_FP_rounding
,
Tag_ABI_FP_denormal
, Tag_ABI_FP_exceptions
,
Tag_ABI_FP_user_exceptions
, Tag_ABI_FP_number_model
,
Tag_ABI_align_needed
, Tag_ABI_align_preserved
,
Tag_ABI_enum_size
, Tag_ABI_HardFP_use
,
Tag_ABI_VFP_args
, Tag_ABI_WMMX_args
,
Tag_ABI_optimization_goals
, Tag_ABI_FP_optimization_goals
,
Tag_compatibility
, Tag_CPU_unaligned_access
,
Tag_FP_HP_extension
, Tag_ABI_FP_16bit_format
,
Tag_MPextension_use
, Tag_DIV_use
,
Tag_nodefaults
, Tag_also_compatible_with
,
Tag_conformance
, Tag_T2EE_use
,
Tag_Virtualization_use
The value is either a number
, "string"
, or
number, "string"
depending on the tag.
Note - the following legacy values are also accepted by tag:
Tag_VFP_arch
, Tag_ABI_align8_needed
,
Tag_ABI_align8_preserved
, Tag_VFP_HP_extension
,
.even
.extend
expression [,
expression]*
.ldouble
expression [,
expression]*
.float16
value [,...,value_n].float16_format
. If the format has not
been explicitly set yet (either via the .float16_format
directive or
the command line option) then the IEEE 754-2008 format is used.
.float16_format
format.float16
directive.
Once the format has been set it cannot be changed.
format
should be one of the following: ieee
(encode in
the IEEE 754-2008 half precision format) or alternative
(encode in
the Arm alternative half precision format).
.fnend
If no personality routine has been specified then standard personality routine 0 or 1 will be used, depending on the number of unwind opcodes required.
.fnstart
.force_thumb
.fpu
name.handlerdata
.fnend
directive will be added to the exception table entry.
Must be preceded by a .personality
or .personalityindex
directive.
.inst
opcode [ , ... ]
.inst.n
opcode [ , ... ]
.inst.w
opcode [ , ... ]
.inst.n
and .inst.w
allow the Thumb instruction size to be
specified explicitly, overriding the normal encoding rules.
.ldouble
expression [,
expression]*
.extend
.
.ltorg
GAS
maintains a separate literal pool for each section and each
sub-section. The .ltorg
directive will only affect the literal
pool of the current section and sub-section. At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.
Note - older versions of GAS
would dump the current literal
pool any time a section change occurred. This is no longer done, since
it prevents accurate control of the placement of literal pools.
.movsp
reg [, #
offset]
.object_arch
name.arch
directive.
Typically this is useful when code uses runtime detection of CPU features.
.packed
expression [,
expression]*
.pad #
count.personality
name.personalityindex
index.pool
.req
register namefoo .req r0
.save
reglist
core registers
.save {r4, r5, r6, lr} stmfd sp!, {r4, r5, r6, lr}
FPA registers
.save f4, 2 sfmfd f4, 2, [sp]!
VFP registers
.save {d8, d9, d10} fstmdx sp!, {d8, d9, d10}
iWMMXt registers
.save {wr10, wr11} wstrd wr11, [sp, #-8]! wstrd wr10, [sp, #-8]! or .save wr11 wstrd wr11, [sp, #-8]! .save wr10 wstrd wr10, [sp, #-8]!
.setfp
fpreg,
spreg [, #
offset]
The syntax of this directive is the same as the add
or mov
instruction used to set the frame pointer. spreg must be either
sp
or mentioned in a previous .movsp
directive.
.movsp ip mov ip, sp ... .setfp fp, ip, #4 add fp, ip, #4
.secrel32
expression [,
expression]*
.syntax [unified | divided]
.thumb
.thumb_func
.thumb
This directive is not necessary when generating EABI objects. On these targets the encoding is implicit when generating Thumb code.
.thumb_set
.set
directive in that it
creates a symbol which is an alias for another symbol (possibly not yet
defined). This directive also has the added property in that it marks
the aliased symbol as being a thumb function entry point, in the same
way that the .thumb_func
directive does.
.tlsdescseq
tls-variable.unreq
alias-namereq
, dn
or qn
directives. For example:
foo .req r0 .unreq foo
An error occurs if the name is undefined. Note - this pseudo op can be used to delete builtin in register name aliases (eg 'r0'). This should only be done if it is really necessary.
.unwind_raw
offset,
byte1, ...
For example .unwind_raw 4, 0xb1, 0x01
is equivalent to
.save {r0}
.vsave
vfp-reglist
VFP registers
.vsave {d8, d9, d10} fstmdd sp!, {d8, d9, d10}
VFPv3 registers
.vsave {d15, d16, d17} vstm sp!, {d15, d16, d17}
Since FLDMX and FSTMX are now deprecated, this directive should be
used in favour of .save
for saving VFP registers for ARMv6 and above.
as
implements all the standard ARM opcodes. It also
implements several pseudo opcodes, including several synthetic load
instructions.
NOP
nop
This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0.
LDR
ldr <register> , = <expression>
If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions. Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.
ADR
adr <register> <label>
This instruction will load the address of label into the indicated register. The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located. If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool.
If label is a thumb function symbol, and thumb interworking has been enabled via the -mthumb-interwork option then the bottom bit of the value stored into register will be set. This allows the following sequence to work as expected:
adr r0, thumb_function blx r0
ADRL
adrl <register> <label>
This instruction will load the address of label into the indicated register. The instruction will evaluate to one or two PC relative ADD or SUB instructions depending upon where the label is located. If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long.
If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.
If label is a thumb function symbol, and thumb interworking has been enabled via the -mthumb-interwork option then the bottom bit of the value stored into register will be set.
For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.
The ARM ELF specification requires that special symbols be inserted into object files to mark certain features:
$a
$t
$d
The assembler will automatically insert these symbols for you - there is no need to code them yourself. Support for tagging symbols ($b, $f, $p and $m) which is also mentioned in the current ARM ELF specification is not implemented. This is because they have been dropped from the new EABI and so tools cannot rely upon their presence.
The ABI for the ARM Architecture specifies a standard format for exception unwind information. This information is used when an exception is thrown to determine where control should be transferred. In particular, the unwind information is used to determine which function called the function that threw the exception, and which function called that one, and so forth. This information is also used to restore the values of callee-saved registers in the function catching the exception.
If you are writing functions in assembly code, and those functions call other functions that throw exceptions, you must use assembly pseudo ops to ensure that appropriate exception unwind information is generated. Otherwise, if one of the functions called by your assembly code throws an exception, the run-time library will be unable to unwind the stack through your assembly code and your program will not behave correctly.
To illustrate the use of these pseudo ops, we will examine the code that G++ generates for the following C++ input:
void callee (int *); int caller () { int i; callee (&i); return i; }
This example does not show how to throw or catch an exception from assembly code. That is a much more complex operation and should always be done in a high-level language, such as C++, that directly supports exceptions.
The code generated by one particular version of G++ when compiling the example above is:
_Z6callerv: .fnstart .LFB2: @ Function supports interworking. @ args = 0, pretend = 0, frame = 8 @ frame_needed = 1, uses_anonymous_args = 0 stmfd sp!, {fp, lr} .save {fp, lr} .LCFI0: .setfp fp, sp, #4 add fp, sp, #4 .LCFI1: .pad #8 sub sp, sp, #8 .LCFI2: sub r3, fp, #8 mov r0, r3 bl _Z6calleePi ldr r3, [fp, #-8] mov r0, r3 sub sp, fp, #4 ldmfd sp!, {fp, lr} bx lr .LFE2: .fnend
Of course, the sequence of instructions varies based on the options you pass to GCC and on the version of GCC in use. The exact instructions are not important since we are focusing on the pseudo ops that are used to generate unwind information.
An important assumption made by the unwinder is that the stack frame
does not change during the body of the function. In particular, since
we assume that the assembly code does not itself throw an exception,
the only point where an exception can be thrown is from a call, such
as the bl
instruction above. At each call site, the same saved
registers (including lr
, which indicates the return address)
must be located in the same locations relative to the frame pointer.
The .fnstart
(see .fnstart pseudo op) pseudo
op appears immediately before the first instruction of the function
while the .fnend
(see .fnend pseudo op) pseudo
op appears immediately after the last instruction of the function.
These pseudo ops specify the range of the function.
Only the order of the other pseudos ops (e.g., .setfp
or
.pad
) matters; their exact locations are irrelevant. In the
example above, the compiler emits the pseudo ops with particular
instructions. That makes it easier to understand the code, but it is
not required for correctness. It would work just as well to emit all
of the pseudo ops other than .fnend
in the same order, but
immediately after .fnstart
.
The .save
(see .save pseudo op) pseudo op
indicates registers that have been saved to the stack so that they can
be restored before the function returns. The argument to the
.save
pseudo op is a list of registers to save. If a register
is “callee-saved” (as specified by the ABI) and is modified by the
function you are writing, then your code must save the value before it
is modified and restore the original value before the function
returns. If an exception is thrown, the run-time library restores the
values of these registers from their locations on the stack before
returning control to the exception handler. (Of course, if an
exception is not thrown, the function that contains the .save
pseudo op restores these registers in the function epilogue, as is
done with the ldmfd
instruction above.)
You do not have to save callee-saved registers at the very beginning
of the function and you do not need to use the .save
pseudo op
immediately following the point at which the registers are saved.
However, if you modify a callee-saved register, you must save it on
the stack before modifying it and before calling any functions which
might throw an exception. And, you must use the .save
pseudo
op to indicate that you have done so.
The .pad
(see .pad) pseudo op indicates a
modification of the stack pointer that does not save any registers.
The argument is the number of bytes (in decimal) that are subtracted
from the stack pointer. (On ARM CPUs, the stack grows downwards, so
subtracting from the stack pointer increases the size of the stack.)
The .setfp
(see .setfp pseudo op) pseudo op
indicates the register that contains the frame pointer. The first
argument is the register that is set, which is typically fp
.
The second argument indicates the register from which the frame
pointer takes its value. The third argument, if present, is the value
(in decimal) added to the register specified by the second argument to
compute the value of the frame pointer. You should not modify the
frame pointer in the body of the function.
If you do not use a frame pointer, then you should not use the
.setfp
pseudo op. If you do not use a frame pointer, then you
should avoid modifying the stack pointer outside of the function
prologue. Otherwise, the run-time library will be unable to find
saved registers when it is unwinding the stack.
The pseudo ops described above are sufficient for writing assembly code that calls functions which may throw exceptions. If you need to know more about the object-file format used to represent unwind information, you may consult the Exception Handling ABI for the ARM Architecture available from http://infocenter.arm.com.
-mmcu=
mcuInstruction set avr1 is for the minimal AVR core, not supported by the C compiler, only for assembler programs (MCU types: at90s1200, attiny11, attiny12, attiny15, attiny28).
Instruction set avr2 (default) is for the classic AVR core with up to 8K program memory space (MCU types: at90s2313, at90s2323, at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534, at90s8535).
Instruction set avr25 is for the classic AVR core with up to 8K program memory space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, attiny828, at86rf401, ata6289, ata5272).
Instruction set avr3 is for the classic AVR core with up to 128K program memory space (MCU types: at43usb355, at76c711).
Instruction set avr31 is for the classic AVR core with exactly 128K program memory space (MCU types: atmega103, at43usb320).
Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP instructions (MCU types: attiny167, attiny1634, at90usb82, at90usb162, atmega8u2, atmega16u2, atmega32u2, ata5505).
Instruction set avr4 is for the enhanced AVR core with up to 8K program memory space (MCU types: atmega48, atmega48a, atmega48pa, atmega48p, atmega8, atmega8a, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6285, ata6286).
Instruction set avr5 is for the enhanced AVR core with up to 128K program memory space (MCU types: at90pwm161, atmega16, atmega16a, atmega161, atmega162, atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega323, atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega32, atmega32a, atmega323, atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, atmega64rfr2, atmega644rfr2, atmega640, atmega644, atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, at90scr100, ata5790, ata5795).
Instruction set avr51 is for the enhanced AVR core with exactly 128K program memory space (MCU types: atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, at90usb1287, m3000).
Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2).
Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5, atxmega8e5, atxmega32e5, atxmega32x1).
Instruction set avrxmega3 is for the XMEGA AVR core with up to 64K of combined program memory and RAM, and with program memory visible in the RAM address space (MCU types: attiny212, attiny214, attiny412, attiny414, attiny416, attiny417, attiny814, attiny816, attiny817, attiny1614, attiny1616, attiny1617, attiny3214, attiny3216, attiny3217).
Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, atxmega64c3, atxmega64d3, atxmega64d4).
Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program memory space and greater than 64K data space (MCU types: atxmega64a1, atxmega64a1u).
Instruction set avrxmega6 is for the XMEGA AVR core with larger than 64K program memory space and less than 64K data space (MCU types: atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4, atxmega192a3, atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3, atxmega192d3, atxmega256a3, atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3, atxmega256d3, atxmega384c3, atxmega256d3).
Instruction set avrxmega7 is for the XMEGA AVR core with larger than 64K program memory space and greater than 64K data space (MCU types: atxmega128a1, atxmega128a1u, atxmega128a4u).
Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 microcontrollers.
-mall-opcodes
-mmcu
.
-mno-skip-bug
-mno-wrap
rjmp/rcall
instructions with 8K wrap-around.
-mrmw
XCH,LAC,LAS,LAT
) instructions.
-mlink-relax
-mno-link-relax
-mgcc-isr
__gcc_isr
pseudo instruction.
The presence of a ‘;’ anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘$’ character can be used instead of a newline to separate statements.
The AVR has 32 x 8-bit general purpose working registers ‘r0’, ‘r1’, ... ‘r31’. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit ‘X’, ‘Y’ and ‘Z’ - registers.
X = r26:r27 Y = r28:r29 Z = r30:r31
The assembler supports several modifiers when using relocatable addresses in AVR instruction operands. The general syntax is the following:
modifier(relocatable-expression)
lo8
hi8
For example
ldi r26, lo8(sym+10) ldi r27, hi8(sym+10)
hh8
hlo8
hhi8
For example
ldi r26, lo8(285774925) ldi r27, hi8(285774925) ldi r28, hlo8(285774925) ldi r29, hhi8(285774925) ; r29,r28,r27,r26 = 285774925
pm_lo8
pm_hi8
pm_hh8
For detailed information on the AVR machine instruction set, see www.atmel.com/products/AVR.
as
implements all the standard AVR opcodes.
The following table summarizes the AVR opcodes, and their arguments.
Legend: r any register d `ldi' register (r16-r31) v `movw' even register (r0, r2, ..., r28, r30) a `fmul' register (r16-r23) w `adiw' register (r24,r26,r28,r30) e pointer registers (X,Y,Z) b base pointer register and displacement ([YZ]+disp) z Z pointer register (for [e]lpm Rd,Z[+]) M immediate value from 0 to 255 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible s immediate value from 0 to 7 P Port address value from 0 to 63. (in, out) p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) K immediate value from 0 to 63 (used in `adiw', `sbiw') i immediate value l signed pc relative offset from -64 to 63 L signed pc relative offset from -2048 to 2047 h absolute code address (call, jmp) S immediate value from 0 to 7 (S = s << 4) ? use this opcode entry if no parameters, else use next opcode entry 1001010010001000 clc 1001010011011000 clh 1001010011111000 cli 1001010010101000 cln 1001010011001000 cls 1001010011101000 clt 1001010010111000 clv 1001010010011000 clz 1001010000001000 sec 1001010001011000 seh 1001010001111000 sei 1001010000101000 sen 1001010001001000 ses 1001010001101000 set 1001010000111000 sev 1001010000011000 sez 100101001SSS1000 bclr S 100101000SSS1000 bset S 1001010100001001 icall 1001010000001001 ijmp 1001010111001000 lpm ? 1001000ddddd010+ lpm r,z 1001010111011000 elpm ? 1001000ddddd011+ elpm r,z 0000000000000000 nop 1001010100001000 ret 1001010100011000 reti 1001010110001000 sleep 1001010110011000 break 1001010110101000 wdr 1001010111101000 spm 000111rdddddrrrr adc r,r 000011rdddddrrrr add r,r 001000rdddddrrrr and r,r 000101rdddddrrrr cp r,r 000001rdddddrrrr cpc r,r 000100rdddddrrrr cpse r,r 001001rdddddrrrr eor r,r 001011rdddddrrrr mov r,r 100111rdddddrrrr mul r,r 001010rdddddrrrr or r,r 000010rdddddrrrr sbc r,r 000110rdddddrrrr sub r,r 001001rdddddrrrr clr r 000011rdddddrrrr lsl r 000111rdddddrrrr rol r 001000rdddddrrrr tst r 0111KKKKddddKKKK andi d,M 0111KKKKddddKKKK cbr d,n 1110KKKKddddKKKK ldi d,M 11101111dddd1111 ser d 0110KKKKddddKKKK ori d,M 0110KKKKddddKKKK sbr d,M 0011KKKKddddKKKK cpi d,M 0100KKKKddddKKKK sbci d,M 0101KKKKddddKKKK subi d,M 1111110rrrrr0sss sbrc r,s 1111111rrrrr0sss sbrs r,s 1111100ddddd0sss bld r,s 1111101ddddd0sss bst r,s 10110PPdddddPPPP in r,P 10111PPrrrrrPPPP out P,r 10010110KKddKKKK adiw w,K 10010111KKddKKKK sbiw w,K 10011000pppppsss cbi p,s 10011010pppppsss sbi p,s 10011001pppppsss sbic p,s 10011011pppppsss sbis p,s 111101lllllll000 brcc l 111100lllllll000 brcs l 111100lllllll001 breq l 111101lllllll100 brge l 111101lllllll101 brhc l 111100lllllll101 brhs l 111101lllllll111 brid l 111100lllllll111 brie l 111100lllllll000 brlo l 111100lllllll100 brlt l 111100lllllll010 brmi l 111101lllllll001 brne l 111101lllllll010 brpl l 111101lllllll000 brsh l 111101lllllll110 brtc l 111100lllllll110 brts l 111101lllllll011 brvc l 111100lllllll011 brvs l 111101lllllllsss brbc s,l 111100lllllllsss brbs s,l 1101LLLLLLLLLLLL rcall L 1100LLLLLLLLLLLL rjmp L 1001010hhhhh111h call h 1001010hhhhh110h jmp h 1001010rrrrr0101 asr r 1001010rrrrr0000 com r 1001010rrrrr1010 dec r 1001010rrrrr0011 inc r 1001010rrrrr0110 lsr r 1001010rrrrr0001 neg r 1001000rrrrr1111 pop r 1001001rrrrr1111 push r 1001010rrrrr0111 ror r 1001010rrrrr0010 swap r 00000001ddddrrrr movw v,v 00000010ddddrrrr muls d,d 000000110ddd0rrr mulsu a,a 000000110ddd1rrr fmul a,a 000000111ddd0rrr fmuls a,a 000000111ddd1rrr fmulsu a,a 1001001ddddd0000 sts i,r 1001000ddddd0000 lds r,i 10o0oo0dddddbooo ldd r,b 100!000dddddee-+ ld r,e 10o0oo1rrrrrbooo std b,r 100!001rrrrree-+ st e,r 1001010100011001 eicall 1001010000011001 eijmp
The only available pseudo-instruction __gcc_isr
can be activated by
option -mgcc-isr.
__gcc_isr 1
tmp_reg
, push of SREG
,
push and clear of zero_reg
, push of Reg.
__gcc_isr 2
zero_reg
,
pop of SREG
, pop of tmp_reg
.
__gcc_isr 0,
RegSREG
, tmp_reg
, zero_reg
.
Prologue chunk and epilogue chunks will be replaced by appropriate code
to save / restore SREG
, tmp_reg
, zero_reg
and Reg.
Example input:
__vector1: __gcc_isr 1 lds r24, var inc r24 sts var, r24 __gcc_isr 2 reti __gcc_isr 0, r24
Example output:
00000000 <__vector1>: 0: 8f 93 push r24 2: 8f b7 in r24, 0x3f 4: 8f 93 push r24 6: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <var> a: 83 95 inc r24 c: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <var> 10: 8f 91 pop r24 12: 8f bf out 0x3f, r24 14: 8f 91 pop r24 16: 18 95 reti
-mcpu=
processor[-
sirevision]-mcpu=
option. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
bf504
,
bf506
,
bf512
,
bf514
,
bf516
,
bf518
,
bf522
,
bf523
,
bf524
,
bf525
,
bf526
,
bf527
,
bf531
,
bf532
,
bf533
,
bf534
,
bf535
(not implemented yet),
bf536
,
bf537
,
bf538
,
bf539
,
bf542
,
bf542m
,
bf544
,
bf544m
,
bf547
,
bf547m
,
bf548
,
bf548m
,
bf549
,
bf549m
,
bf561
,
and
bf592
.
-mfdpic
-mno-fdpic
-mnopic
Special Characters
Comments are introduced by the ‘#’ character and extend to the
end of the current line. If the ‘#’ appears as the first
character of a line, the whole line is treated as a comment, but in
this case the line can also be a logical line number directive
(see Comments) or a preprocessor control command
(see Preprocessing).
Instruction Delimiting
a0= r3.h * r2.l, a1 = r3.l * r2.h ;
The second case occurs when a general instruction is combined with one or two memory references for joint issue. The latter portions are set off by a "||" token.
a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
Multiple instructions can occur on the same line. Each must be
terminated by a semicolon character.
Register Names
Register names are reserved and may not be used as program identifiers.
Some operations (such as "Move Register") require a register pair. Register pairs are always data registers and are denoted using a colon, eg., R3:2. The larger number must be written firsts. Note that the hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
Some instructions (such as –SP (Push Multiple)) require a group of adjacent registers. Adjacent registers are denoted in the syntax by the range enclosed in parentheses and separated by a colon, eg., (R7:3). Again, the larger number appears first.
Portions of a particular register may be individually specified. This
is written with a dot (".") following the register name and then a
letter denoting the desired portion. For 32-bit registers, ".H"
denotes the most significant ("High") portion. ".L" denotes the
least-significant portion. The subdivisions of the 40-bit registers
are described later.
Accumulators
one 40-bit register
one 32-bit register
two 16-bit registers
one 8-bit register
Data Registers
R7.L, r2.h, r4.L, R0.H
Pointer Registers
p2, p5, fp, sp
Stack Pointer SP
Frame Pointer FP
Loop Top
Loop Count
Loop Bottom
Index Registers
Modify Registers
Length Registers
Base Registers
Floating Point
Blackfin Opcodes
The following directives are provided for compatibility with the VDSP assembler.
.byte2
This maps to the .short
directive.
.byte4
This maps to the .int
directive.
.db
This directive is a synonym for .byte
.
.dw
This directive is a synonym for .byte2
.
.dd
This directive is a synonym for .byte4
.
.var
The National Semiconductor CR16 target of as
has a few machine dependent operand qualifiers.
Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The @
is required. CR16 architecture uses one of the following expression qualifiers:
s
Specifies expression operand type as small
m
Specifies expression operand type as medium
l
Specifies expression operand type as large
c
Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.
got/GOT
Specifies the CR16 Assembler generates a relocation entry for the operand, offset from Global Offset Table. The linker uses this relocation entry to update the operand address at link time
cgot/cGOT
Specifies the CompactRISC Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.
CR16 target operand qualifiers and its size (in bits):
For example:
1movw $_myfun@c,r1
This loads the address of _myfun, shifted right by 1, into r1. 2movd $_myfun@c,(r2,r1)
This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 3_myfun_ptr:
.long _myfun@c
loadd _myfun_ptr, (r1,r0)
jal (r1,r0)
This .long directive, the address of _myfunc, shifted right by 1 at link time. 4loadd _data1@GOT(r12), (r1,r0)
This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 5loadd _myfunc@cGOT(r12), (r1,r0)
This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
The presence of a ‘#’ on a line indicates the start of a comment that extends to the end of the current line. If the ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘;’ character can be used to separate statements on the same line.
The CRIS version of as
has these
machine-dependent command-line options.
The format of the generated object files can be either ELF or
a.out, specified by the command-line options
--emulation=crisaout and --emulation=criself.
The default is ELF (criself), unless as
has been
configured specifically for a.out by using the configuration
name cris-axis-aout
.
There are two different link-incompatible ELF object file variants for CRIS, for use in environments where symbols are expected to be prefixed by a leading ‘_’ character and for environments without such a symbol prefix. The variant used for GNU/Linux port has no symbol prefix. Which variant to produce is specified by either of the options --underscore and --no-underscore. The default is --underscore. Since symbols in CRIS a.out objects are expected to have a ‘_’ prefix, specifying --no-underscore when generating a.out objects is an error. Besides the object format difference, the effect of this option is to parse register names differently (see crisnous). The --no-underscore option makes a ‘$’ register prefix mandatory.
The option --pic must be passed to as
in
order to recognize the symbol syntax used for ELF (SVR4 PIC)
position-independent-code (see crispic). This will also
affect expansion of instructions. The expansion with
--pic will use PC-relative rather than (slightly
faster) absolute addresses in those expansions. This option is only
valid when generating ELF format object files.
The option --march=architecture specifies the recognized instruction set and recognized register names. It also controls the architecture type of the object file. Valid values for architecture are:
v0_v10
v10
v32
common_v10_v32
When -N is specified, as
will emit a
warning when a 16-bit branch instruction is expanded into a
32-bit multiple-instruction construct (see CRIS-Expand).
Some versions of the CRIS v10, for example in the Etrax 100 LX,
contain a bug that causes destabilizing memory accesses when a
multiply instruction is executed with certain values in the
first operand just before a cache-miss. When the
--mul-bug-abort command-line option is active (the
default value), as
will refuse to assemble a file
containing a multiply instruction at a dangerous offset, one
that could be the last on a cache-line, or is in a section with
insufficient alignment. This placement checking does not catch
any case where the multiply instruction is dangerously placed
because it is located in a delay-slot. The
--mul-bug-abort command-line option turns off the
checking.
as
will silently choose an instruction that fits
the operand size for ‘[register+constant]’ operands. For
example, the offset 127
in move.d [r3+127],r4
fits
in an instruction using a signed-byte offset. Similarly,
move.d [r2+32767],r1
will generate an instruction using a
16-bit offset. For symbolic expressions and constants that do
not fit in 16 bits including the sign bit, a 32-bit offset is
generated.
For branches, as
will expand from a 16-bit branch
instruction into a sequence of instructions that can reach a
full 32-bit address. Since this does not correspond to a single
instruction, such expansions can optionally be warned about.
See CRIS-Opts.
If the operand is found to fit the range, a lapc
mnemonic
will translate to a lapcq
instruction. Use lapc.d
to force the 32-bit lapc
instruction.
Similarly, the addo
mnemonic will translate to the
shortest fitting instruction of addoq
, addo.w
and
addo.d
, when used with a operand that is a constant known
at assembly time.
Some symbols are defined by the assembler. They're intended to be used in conditional assembly, for example:
.if ..asm.arch.cris.v32 code for CRIS v32 .elseif ..asm.arch.cris.common_v10_v32 code common to CRIS v32 and CRIS v10 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 code for v10 .else .error "Code needs to be added here." .endif
These symbols are defined in the assembler, reflecting command-line options, either when specified or the default. They are always defined, to 0 or 1.
..asm.arch.cris.any_v0_v10
..asm.arch.cris.common_v10_v32
..asm.arch.cris.v10
..asm.arch.cris.v32
Speaking of symbols, when a symbol is used in code, it can have a suffix modifying its value for use in position-independent code. See CRIS-Pic.
There are different aspects of the CRIS assembly syntax.
The character ‘#’ is a line comment character. It starts a comment if and only if it is placed at the beginning of a line.
A ‘;’ character starts a comment anywhere on the line, causing all characters up to the end of the line to be ignored.
A ‘@’ character is handled as a line separator equivalent to a logical new-line character (except in a comment), so separate instructions can be specified on a single line.
When generating position-independent code (SVR4
PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu
shared libraries, symbol
suffixes are used to specify what kind of run-time symbol lookup
will be used, expressed in the object as different
relocation types. Usually, all absolute symbol values
must be located in a table, the global offset table,
leaving the code position-independent; independent of values of
global symbols and independent of the address of the code. The
suffix modifies the value of the symbol, into for example an
index into the global offset table where the real symbol value
is entered, or a PC-relative value, or a value relative to the
start of the global offset table. All symbol suffixes start
with the character ‘:’ (omitted in the list below). Every
symbol use in code or a read-only section must therefore have a
PIC suffix to enable a useful shared library to be created.
Usually, these constructs must not be used with an additive
constant offset as is usually allowed, i.e. no 4 as in
symbol + 4
is allowed. This restriction is checked at
link-time, not at assembly-time.
GOT
move.d
[$r0+extsym:GOT],$r9
GOT16
move.d
[$r0+asymbol:GOT16],$r10
PLT
add.d fnname:PLT,$pc
PLTG
move.d
fnname:PLTG,$r3
GOTPLT
jsr
[$r0+fnname:GOTPLT]
GOTPLT16
jsr
[$r0+fnname:GOTPLT16]
GOTOFF
move.d [$r0+localsym:GOTOFF],r3
A ‘$’ character may always prefix a general or special
register name in an instruction operand but is mandatory when
the option --no-underscore is specified or when the
.syntax register_prefix
directive is in effect
(see crisnous). Register names are case-insensitive.
There are a few CRIS-specific pseudo-directives in addition to the generic ones. See Pseudo Ops. Constants emitted by pseudo-directives are in little-endian order for CRIS. There is no support for floating-point-specific directives for CRIS.
.dword EXPRESSIONS
.dword
directive is a synonym for .int
,
expecting zero or more EXPRESSIONS, separated by commas. For
each expression, a 32-bit little-endian constant is emitted.
.syntax ARGUMENT
.syntax
directive takes as ARGUMENT one of the
following case-sensitive choices.
no_register_prefix
.syntax no_register_prefix
directive
makes a ‘$’ character prefix on all registers optional. It
overrides a previous setting, including the corresponding effect
of the option --no-underscore. If this directive is
used when ordinary symbols do not have a ‘_’ character
prefix, care must be taken to avoid ambiguities whether an
operand is a register or a symbol; using symbols with names the
same as general or special registers then invoke undefined
behavior.
register_prefix
leading_underscore
no_leading_underscore
.syntax leading_underscore
directive and emits an error if the option --underscore
is in effect.
.arch ARGUMENT
The Mitsubishi D10V version of as
has a few machine
dependent options.
as
will attempt to optimize its output by detecting when
instructions can be executed in parallel.
as
will sometimes swap the
order of instructions. Normally this generates a warning. When this option
is used, no warning will be generated when instructions are swapped.
as
packs adjacent short instructions into a single packed
instruction. ‘--no-gstabs-packing’ turns instruction packing off if
‘--gstabs’ is specified as well; ‘--gstabs-packing’ (the
default) turns instruction packing on even when ‘--gstabs’ is
specified.
The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below.
The D10V version of as
uses the instruction names in the D10V
Architecture Manual. However, the names in the manual are sometimes ambiguous.
There are instruction names that can assemble to a short or long form opcode.
How does the assembler pick the correct form? as
will always pick the
smallest form if it can. When dealing with a symbol that is not defined yet when a
line is being assembled, it will always use the long form. If you need to force the
assembler to use either the short or long form of the instruction, you can append
either ‘.s’ (short) or ‘.l’ (long) to it. For example, if you are writing
an assembly program and you want to do a branch to a symbol that is defined later
in your program, you can write ‘bra.s foo’.
Objdump and GDB will always append ‘.s’ or ‘.l’ to instructions which
have both short and long forms.
The D10V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the previous one. Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid. Nops are automatically inserted when necessary.
If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.
A semicolon (‘;’) can be used anywhere on a line to start a comment that extends to the end of the line.
If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially. To specify the executing order, use the following symbols:
abs a1 -> abs r0
abs r0 <- abs a1
ld2w r2,@r8+ || mac a0,r0,r7
ld2w r2,@r8+ ||
mac a0,r0,r7
ld2w r2,@r8+
mac a0,r0,r7
ld2w r2,@r8+ ->
mac a0,r0,r7
You can use the predefined symbols ‘r0’ through ‘r15’ to refer to the D10V registers. You can also use ‘sp’ as an alias for ‘r15’. The accumulators are ‘a0’ and ‘a1’. There are special register-pair names that may optionally be used in opcodes that require even-numbered registers. Register names are not case sensitive.
Register Pairs
r0-r1
r2-r3
r4-r5
r6-r7
r8-r9
r10-r11
r12-r13
r14-r15
The D10V also has predefined symbols for these control registers and status bits:
psw
bpsw
pc
bpc
rpt_c
rpt_s
rpt_e
mod_s
mod_e
iba
f0
f1
c
as
understands the following addressing modes for the D10V.
R
n in the following refers to any of the numbered
registers, but not the control registers.
R
n@R
n@R
n+
@R
n-
@-SP
@(
disp, R
n)
#
immAny symbol followed by @word
will be replaced by the symbol's value
shifted right by 2. This is used in situations such as loading a register
with the address of a function (or any other code fragment). For example, if
you want to load a register with the location of the function main
then
jump to that function, you could do it as follows:
ldi r2, main@word jmp r2
The D10V has no hardware floating point, but the .float
and .double
directives generates ieee floating-point numbers for compatibility
with other development tools.
For detailed information on the D10V machine instruction set, see
D10V Architecture: A VLIW Microprocessor for Multimedia Applications
(Mitsubishi Electric Corp.).
as
implements all the standard D10V opcodes. The only changes are those
described in the section on size modifiers
The Mitsubishi D30V version of as
has a few machine
dependent options.
as
will attempt to optimize its output by detecting when
instructions can be executed in parallel.
as
will issue a warning every
time it adds a nop instruction.
as
will issue a warning if it
needs to insert a nop after a 32-bit multiply before a load or 16-bit
multiply instruction.
The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below.
The D30V version of as
uses the instruction names in the D30V
Architecture Manual. However, the names in the manual are sometimes ambiguous.
There are instruction names that can assemble to a short or long form opcode.
How does the assembler pick the correct form? as
will always pick the
smallest form if it can. When dealing with a symbol that is not defined yet when a
line is being assembled, it will always use the long form. If you need to force the
assembler to use either the short or long form of the instruction, you can append
either ‘.s’ (short) or ‘.l’ (long) to it. For example, if you are writing
an assembly program and you want to do a branch to a symbol that is defined later
in your program, you can write ‘bra.s foo’.
Objdump and GDB will always append ‘.s’ or ‘.l’ to instructions which
have both short and long forms.
The D30V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the previous one. Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid. Nops are automatically inserted when necessary.
If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.
A semicolon (‘;’) can be used anywhere on a line to start a comment that extends to the end of the line.
If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially unless you use the ‘-O’ option.
To specify the executing order, use the following symbols:
The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example
abs r2,r3 -> abs r4,r5
abs r2,r3 <- abs r4,r5
abs r2,r3 || abs r4,r5
ldw r2,@(r3,r4) ||
mulx r6,r8,r9
mulx a0,r8,r9
stw r2,@(r3,r4)
stw r2,@(r3,r4) ->
mulx a0,r8,r9
stw r2,@(r3,r4) <-
mulx a0,r8,r9
Since ‘$’ has no special meaning, you may use it in symbol names.
as
supports the full range of guarded execution
directives for each instruction. Just append the directive after the
instruction proper. The directives are:
You can use the predefined symbols ‘r0’ through ‘r63’ to refer to the D30V registers. You can also use ‘sp’ as an alias for ‘r63’ and ‘link’ as an alias for ‘r62’. The accumulators are ‘a0’ and ‘a1’.
The D30V also has predefined symbols for these control registers and status bits:
psw
bpsw
pc
bpc
rpt_c
rpt_s
rpt_e
mod_s
mod_e
iba
f0
f1
f2
f3
f4
f5
f6
f7
s
v
va
c
b
as
understands the following addressing modes for the D30V.
R
n in the following refers to any of the numbered
registers, but not the control registers.
R
n@R
n@R
n+
@R
n-
@-SP
@(
disp, R
n)
#
immThe D30V has no hardware floating point, but the .float
and .double
directives generates ieee floating-point numbers for compatibility
with other development tools.
For detailed information on the D30V machine instruction set, see
D30V Architecture: A VLIW Microprocessor for Multimedia Applications
(Mitsubishi Electric Corp.).
as
implements all the standard D30V opcodes. The only changes are those
described in the section on size modifiers
as
has two additional command-line options for the Epiphany
architecture.
-mepiphany
-mepiphany16
The presence of a ‘;’ on a line indicates the start of a comment that extends to the end of the current line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘`’ character can be used to separate statements on the same line.
The Renesas H8/300 version of as
has one
machine-dependent option:
-h-tick-hex
-mach=
nameh8300h
,
h8300hn
,
h8300s
,
h8300sn
,
h8300sx
and
h8300sxn
.
‘;’ is the line comment character.
‘$’ can be used instead of a newline to separate statements. Therefore you may not use ‘$’ in symbol names on the H8/300.
You can use predefined symbols of the form ‘rnh’ and ‘rnl’ to refer to the H8/300 registers as sixteen 8-bit general-purpose registers. n is a digit from ‘0’ to ‘7’); for instance, both ‘r0h’ and ‘r7l’ are valid register names.
You can also use the eight predefined symbols ‘rn’ to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).
On the H8/300H, you can also use the eight predefined symbols ‘ern’ (‘er0’ ... ‘er7’) to refer to the 32-bit general purpose registers.
The two control registers are called pc
(program counter; a
16-bit register, except on the H8/300H where it is 24 bits) and
ccr
(condition code register; an 8-bit register). r7
is
used as the stack pointer, and can also be called sp
.
as understands the following addressing modes for the H8/300:
r
n@r
n@(
d, r
n)
@(
d:16, r
n)
@(
d:24, r
n)
@r
n+
@-r
n@
aa@
aa:8
@
aa:16
@
aa:24
aa
. (The address size ‘:24’ only makes
sense on the H8/300H.)
#
xx#
xx:8
#
xx:16
#
xx:32
as
neither
requires this nor uses it—the data size required is taken from
context.
@@
aa@@
aa:8
as
neither requires this nor uses it.
The H8/300 family has no hardware floating point, but the .float
directive generates ieee floating-point numbers for compatibility
with other development tools.
as
has the following machine-dependent directives for
the H8/300:
.h8300h
.int
emit 32-bit numbers rather than the usual (16-bit)
for the H8/300 family.
.h8300s
.int
emit 32-bit numbers rather than the usual (16-bit)
for the H8/300 family.
.h8300hn
.int
emit 32-bit numbers rather than
the usual (16-bit) for the H8/300 family.
.h8300sn
.int
emit 32-bit numbers rather than
the usual (16-bit) for the H8/300 family.
On the H8/300 family (including the H8/300H) ‘.word’ directives generate 16-bit numbers.
For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual. For information specific to the H8/300H, see H8/300H Series Programming Manual (Renesas).
as
implements all the standard H8/300 opcodes. No additional
pseudo-instructions are needed on this family.
Four H8/300 instructions (add
, cmp
, mov
,
sub
) are defined with variants using the suffixes ‘.b’,
‘.w’, and ‘.l’ to specify the size of a memory operand.
as
supports these suffixes, but does not require them;
since one of the operands is always a register, as
can
deduce the correct size.
For example, since r0
refers to a 16-bit register,
mov r0,@foo
is equivalent to
mov.w r0,@foo
If you use the size suffixes, as
issues a warning when
the suffix and the register size do not match.
As a back end for gnu cc as
has been thoroughly tested and should
work extremely well. We have tested it only minimally on hand written assembly
code and no one has tested it much on the assembly output from the HP
compilers.
The format of the debugging sections has changed since the original
as
port (version 1.3X) was released; therefore,
you must rebuild all HPPA objects and libraries with the new
assembler so that you can debug the final executable.
The HPPA as
port generates a small subset of the relocations
available in the SOM and ELF object file formats. Additional relocation
support will be added as it becomes necessary.
as
has no machine-dependent command-line options for the HPPA.
The assembler syntax closely follows the HPPA instruction set reference manual; assembler directives and general syntax closely follow the HPPA assembly language reference manual, with a few noteworthy differences.
First, a colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.
Some obscure expression parsing problems may affect hand written code which
uses the spop
instructions, or code which makes significant
use of the !
line separator.
as
is much less forgiving about missing arguments and other
similar oversights than the HP assembler. as
notifies you
of missing arguments as syntax errors; this is regarded as a feature, not a
bug.
Finally, as
allows you to use an external symbol without
explicitly importing the symbol. Warning: in the future this will be
an error for HPPA targets.
Special characters for HPPA targets include:
‘;’ is the line comment character.
‘!’ can be used instead of a newline to separate statements.
Since ‘$’ has no special meaning, you may use it in symbol names.
The HPPA family uses ieee floating-point numbers.
as
for the HPPA supports many additional directives for
compatibility with the native assembler. This section describes them only
briefly. For detailed information on HPPA-specific assembler directives, see
HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001).
as
does not support the following assembler directives
described in the HP manual:
.endm .liston .enter .locct .leave .macro .listoff
Beyond those implemented for compatibility, as
supports one
additional assembler directive for the HPPA: .param
. It conveys
register argument locations for static functions. Its syntax closely follows
the .export
directive.
These are the additional directives in as
for the HPPA:
.block
n.blockz
n.call
.callinfo [
param=
value, ... ] [
flag, ... ]
param may be any of ‘frame’ (frame size), ‘entry_gr’ (end of general register range), ‘entry_fr’ (end of float register range), ‘entry_sr’ (end of space register range).
The values for flag are ‘calls’ or ‘caller’ (proc has
subroutines), ‘no_calls’ (proc does not call subroutines), ‘save_rp’
(preserve return pointer), ‘save_sp’ (proc preserves stack pointer),
‘no_unwind’ (do not unwind this proc), ‘hpux_int’ (proc is interrupt
routine).
.code
.copyright "
string"
.copyright "
string"
.enter
.entry
.exit
.export
name [ ,
typ ] [ ,
param=
r ]
param, if present, provides either relocation information for the
procedure arguments and result, or a privilege level. param may be
‘argwn’ (where n ranges from 0
to 3
, and
indicates one of four one-word arguments); ‘rtnval’ (the procedure's
result); or ‘priv_lev’ (privilege level). For arguments or the result,
r specifies how to relocate, and must be one of ‘no’ (not
relocatable), ‘gr’ (argument is in general register), ‘fr’ (in
floating point register), or ‘fu’ (upper half of float register).
For ‘priv_lev’, r is an integer.
.half
nas
directive .short
.
.import
name [ ,
typ ]
.export
; make a procedure available to call. The arguments
use the same conventions as the first two arguments for .export
.
.label
name.leave
.origin
lcas
portable directive .org
.
.param
name [ ,
typ ] [ ,
param=
r ]
.export
, but used for static procedures.
.proc
.procend
.reg
expr.equ
; define label with the absolute expression
expr as its value.
.space
secname [ ,
params ]
If specified, the list params declares attributes of the section,
identified by keywords. The keywords recognized are ‘spnum=exp’
(identify this section by the number exp, an absolute expression),
‘sort=exp’ (order sections according to this sort key when linking;
exp is an absolute expression), ‘unloadable’ (section contains no
loadable data), ‘notdefined’ (this section defined elsewhere), and
‘private’ (data in this section not available to other programs).
.spnum
secnam.space
directive.)
.string "
str"
as
strings.
Warning! The HPPA version of .string
differs from the
usual as
definition: it does not write a zero byte
after copying str.
.stringz "
str"
.string
, but appends a zero byte after copying str to object
file.
.subspa
name [ ,
params ]
.nsubspa
name [ ,
params ]
.space
, but selects a subsection name within the
current section. You may only specify params when you create a
subsection (in the first instance of .subspa
for this name).
If specified, the list params declares attributes of the subsection, identified by keywords. The keywords recognized are ‘quad=expr’ (“quadrant” for this subsection), ‘align=expr’ (alignment for beginning of this subsection; a power of two), ‘access=expr’ (value for “access rights” field), ‘sort=expr’ (sorting order for this subspace in link), ‘code_only’ (subsection contains only code), ‘unloadable’ (subsection cannot be loaded into memory), ‘comdat’ (subsection is comdat), ‘common’ (subsection is common block), ‘dup_comm’ (subsection may have duplicate names), or ‘zero’ (subsection is all zeros, do not write in object file).
.nsubspa
always creates a new subspace with the given name, even
if one with the same name already exists.
‘comdat’, ‘common’ and ‘dup_comm’ can be used to implement various flavors of one-only support when using the SOM linker. The SOM linker only supports specific combinations of these flags. The details are not documented. A brief description is provided here.
‘comdat’ provides a form of linkonce support. It is useful for both code and data subspaces. A ‘comdat’ subspace has a key symbol marked by the ‘is_comdat’ flag or ‘ST_COMDAT’. Only the first subspace for any given key is selected. The key symbol becomes universal in shared links. This is similar to the behavior of ‘secondary_def’ symbols.
‘common’ provides Fortran named common support. It is only useful for data subspaces. Symbols with the flag ‘is_common’ retain this flag in shared links. Referencing a ‘is_common’ symbol in a shared library from outside the library doesn't work. Thus, ‘is_common’ symbols must be output whenever they are needed.
‘common’ and ‘dup_comm’ together provide Cobol common support. The subspaces in this case must all be the same length. Otherwise, this support is similar to the Fortran common support.
‘dup_comm’ by itself provides a type of one-only support for code. Only the first ‘dup_comm’ subspace is selected. There is a rather complex algorithm to compare subspaces. Code symbols marked with the ‘dup_common’ flag are hidden. This support was intended for "C++ duplicate inlines".
A simplified technique is used to mark the flags of symbols based on
the flags of their subspace. A symbol with the scope SS_UNIVERSAL and
type ST_ENTRY, ST_CODE or ST_DATA is marked with the corresponding
settings of ‘comdat’, ‘common’ and ‘dup_comm’ from the
subspace, respectively. This avoids having to introduce additional
directives to mark these symbols. The HP assembler sets ‘is_common’
from ‘common’. However, it doesn't set the ‘dup_common’ from
‘dup_comm’. It doesn't have ‘comdat’ support.
.version "
str"
For detailed information on the HPPA machine instruction set, see PA-RISC Architecture and Instruction Set Reference Manual (HP 09740-90039).
The i386 version as
supports both the original Intel 386
architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
extending the Intel architecture to 64-bits.
The i386 version of as
has a few machine
dependent options:
--32 | --x32 | --64
These options are only available with the ELF object file format, and
require that the necessary BFD support has been included (on a 32-bit
platform you have to add –enable-64-bit-bfd to configure enable 64-bit
usage and use x86-64 as target platform).
-n
--divide
-march=
CPU[+
EXTENSION...]
i8086
,
i186
,
i286
,
i386
,
i486
,
i586
,
i686
,
pentium
,
pentiumpro
,
pentiumii
,
pentiumiii
,
pentium4
,
prescott
,
nocona
,
core
,
core2
,
corei7
,
l1om
,
k1om
,
iamcu
,
k6
,
k6_2
,
athlon
,
opteron
,
k8
,
amdfam10
,
bdver1
,
bdver2
,
bdver3
,
bdver4
,
znver1
,
znver2
,
btver1
,
btver2
,
generic32
and
generic64
.
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics. For example,
-march=i686+sse4+vmx
extends i686 with sse4 and
vmx. The following extensions are currently supported:
8087
,
287
,
387
,
687
,
no87
,
no287
,
no387
,
no687
,
cmov
,
nocmov
,
fxsr
,
nofxsr
,
mmx
,
nommx
,
sse
,
sse2
,
sse3
,
ssse3
,
sse4.1
,
sse4.2
,
sse4
,
nosse
,
nosse2
,
nosse3
,
nossse3
,
nosse4.1
,
nosse4.2
,
nosse4
,
avx
,
avx2
,
noavx
,
noavx2
,
adx
,
rdseed
,
prfchw
,
smap
,
mpx
,
sha
,
rdpid
,
ptwrite
,
cet
,
gfni
,
vaes
,
vpclmulqdq
,
prefetchwt1
,
clflushopt
,
se1
,
clwb
,
movdiri
,
movdir64b
,
enqcmd
,
avx512f
,
avx512cd
,
avx512er
,
avx512pf
,
avx512vl
,
avx512bw
,
avx512dq
,
avx512ifma
,
avx512vbmi
,
avx512_4fmaps
,
avx512_4vnniw
,
avx512_vpopcntdq
,
avx512_vbmi2
,
avx512_vnni
,
avx512_bitalg
,
avx512_bf16
,
noavx512f
,
noavx512cd
,
noavx512er
,
noavx512pf
,
noavx512vl
,
noavx512bw
,
noavx512dq
,
noavx512ifma
,
noavx512vbmi
,
noavx512_4fmaps
,
noavx512_4vnniw
,
noavx512_vpopcntdq
,
noavx512_vbmi2
,
noavx512_vnni
,
noavx512_bitalg
,
noavx512_vp2intersect
,
noavx512_bf16
,
noenqcmd
,
vmx
,
vmfunc
,
smx
,
xsave
,
xsaveopt
,
xsavec
,
xsaves
,
aes
,
pclmul
,
fsgsbase
,
rdrnd
,
f16c
,
bmi2
,
fma
,
movbe
,
ept
,
lzcnt
,
hle
,
rtm
,
invpcid
,
clflush
,
mwaitx
,
clzero
,
wbnoinvd
,
pconfig
,
waitpkg
,
cldemote
,
rdpru
,
mcommit
,
lwp
,
fma4
,
xop
,
cx16
,
syscall
,
rdtscp
,
3dnow
,
3dnowa
,
sse4a
,
sse5
,
svme
,
abm
and
padlock
.
Note that rather than extending a basic instruction set, the extension
mnemonics starting with no
revoke the respective functionality.
When the .arch
directive is used with -march, the
.arch
directive will take precedent.
-mtune=
CPUValid CPU values are identical to the processor list of -march=CPU.
-msse2avx
-msse-check=
none-msse-check=
warning-msse-check=
error-mavxscalar=
128-mavxscalar=
256WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models.
-mvexwig=
0-mvexwig=
1WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models.
-mevexlig=
128-mevexlig=
256-mevexlig=
512-mevexwig=
0-mevexwig=
1-mmnemonic=
att-mmnemonic=
intel.att_mnemonic
and .intel_mnemonic
directives will
take precedent.
-msyntax=
att-msyntax=
intel.att_syntax
and .intel_syntax
directives will
take precedent.
-mnaked-reg
.att_syntax
and .intel_syntax
directives will take precedent.
-madd-bnd-prefix
-mno-shared
-mbig-obj
-momit-lock-prefix=
no-momit-lock-prefix=
yes-mfence-as-lock-add=
no-mfence-as-lock-add=
yes-mrelax-relocations=
no-mrelax-relocations=
yes-mx86-used-note=
no-mx86-used-note=
yes-mevexrcig=
rne-mevexrcig=
rd-mevexrcig=
ru-mevexrcig=
rz-mamd64
-mintel64
-O0 | -O | -O1 | -O2 | -Os
‘-O2’ includes ‘-O1’ optimization plus encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions. In 64-bit mode VEX encoded instructions with commutative source operands will also have their source operands swapped if this allows using the 2-byte VEX prefix form instead of the 3-byte one. Certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST.
‘-Os’ includes ‘-O2’ optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. ‘-O0’ turns off this optimization.
.lcomm
symbol ,
length[,
alignment]
ld
. The optional third parameter, alignment,
specifies the desired alignment of the symbol in the bss section.
This directive is only available for COFF based x86 targets.
.largecomm
symbol ,
length[,
alignment]
comm
directive
except that the data is placed into the .lbss section instead of
the .bss section Comm.
The directive is intended to be used for data which requires a large amount of space, and it is only available for ELF based x86_64 targets.
.value
expression [,
expression]
.short
directive,
taking a series of comma separated expressions and storing them as
two-byte wide values into the current section.
as
now supports assembly using Intel assembler syntax.
.intel_syntax
selects Intel mode, and .att_syntax
switches
back to the usual AT&T mode for compatibility with the output of
gcc
. Either of these directives may have an optional
argument, prefix
, or noprefix
specifying whether registers
require a ‘%’ prefix. AT&T System V/386 assembler syntax is quite
different from Intel syntax. We mention these differences because
almost all 80386 documents use Intel syntax. Notable differences
between the two syntaxes are:
In 64-bit code, ‘movabs’ can be used to encode the ‘mov’ instruction with the 64-bit displacement or immediate operand.
The presence of a ‘#’ appearing anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
If the --divide command-line option has not been specified then the ‘/’ character appearing anywhere on a line also introduces a line comment.
The ‘;’ character can be used to separate statements on the same line.
Instruction mnemonics are suffixed with one character modifiers which
specify the size of operands. The letters ‘b’, ‘w’, ‘l’
and ‘q’ specify byte, word, long and quadruple word operands. If
no suffix is specified by an instruction then as
tries to
fill in the missing suffix based on the destination register operand
(the last one by convention). Thus, ‘mov %ax, %bx’ is equivalent
to ‘movw %ax, %bx’; also, ‘mov $1, %bx’ is equivalent to
‘movw $1, bx’. Note that this is incompatible with the AT&T Unix
assembler which assumes that a missing mnemonic suffix implies long
operand size. (This incompatibility does not affect compiler output
since compilers always explicitly specify the mnemonic suffix.)
Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are ‘movs...’ and ‘movz...’ in AT&T syntax (‘movsx’ and ‘movzx’ in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, ‘movsbl %al, %edx’ is AT&T syntax for “move sign extend from %al to %edx.” Possible suffixes, thus, are ‘bl’ (from byte to long), ‘bw’ (from byte to word), ‘wl’ (from word to long), ‘bq’ (from byte to quadruple word), ‘wq’ (from word to quadruple word), and ‘lq’ (from long to quadruple word).
Different encoding options can be specified via pseudo prefixes:
The Intel-syntax conversion instructions
are called ‘cbtw’, ‘cwtl’, ‘cwtd’, ‘cltd’, ‘cltq’, and
‘cqto’ in AT&T naming. as
accepts either naming for these
instructions.
Far call/jump instructions are ‘lcall’ and ‘ljmp’ in AT&T syntax, but are ‘call far’ and ‘jump far’ in Intel convention.
as
supports assembly using Intel mnemonic.
.intel_mnemonic
selects Intel mnemonic with Intel syntax, and
.att_mnemonic
switches back to the usual AT&T mnemonic with AT&T
syntax for compatibility with the output of gcc
.
Several x87 instructions, ‘fadd’, ‘fdiv’, ‘fdivp’,
‘fdivr’, ‘fdivrp’, ‘fmul’, ‘fsub’, ‘fsubp’,
‘fsubr’ and ‘fsubrp’, are implemented in AT&T System V/386
assembler with different mnemonics from those in Intel IA32 specification.
gcc
generates those instructions with AT&T mnemonic.
Register operands are always prefixed with ‘%’. The 80386 registers consist of
The AMD x86-64 architecture extends the register set by:
With the AVX extensions more registers were made available:
The AVX2 extensions made in 64-bit mode more registers available:
The AVX512 extensions added the following registers:
Instruction prefixes are used to modify the following instruction. They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an “operand size” prefix.) Instruction prefixes are best written on the same line as the instruction they act upon. For example, the ‘scas’ (scan string) instruction is repeated with:
repne scas %es:(%edi),%al
You may also place prefixes on the lines immediately preceding the
instruction, but this circumvents checks that as
does
with prefixes, and will not work with all prefixes.
Here is a list of instruction prefixes:
.code16
section) into 32-bit operands/addresses. These prefixes
must appear on the same line of code as the instruction they
modify. For example, in a 16-bit .code16
section, you might
write:
addr32 jmpl *(%ebx)
64
) used to change operand size
from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
register set.
You may write the ‘rex’ prefixes directly. The ‘rex64xyz’
instruction emits ‘rex’ prefix with all the bits set. By omitting
the 64
, x
, y
or z
you may write other
prefixes as well. Normally, there is no need to write the prefixes
explicitly, since gas will automatically generate them based on the
instruction operands.
An Intel syntax indirect memory reference of the form
section:[base + index*scale + disp]
is translated into the AT&T syntax
section:disp(base, index, scale)
where base and index are the optional 32-bit base and
index registers, disp is the optional displacement, and
scale, taking the values 1, 2, 4, and 8, multiplies index
to calculate the address of the operand. If no scale is
specified, scale is taken to be 1. section specifies the
optional section register for the memory operand, and may override the
default section register (see a 80386 manual for section register
defaults). Note that section overrides in AT&T syntax must
be preceded by a ‘%’. If you specify a section override which
coincides with the default section register, as
does not
output any section register override prefixes to assemble the given
instruction. Thus, section overrides can be specified to emphasize which
section register is used for a given memory operand.
Here are some examples of Intel and AT&T style memory references:
Absolute (as opposed to PC relative) call and jump operands must be
prefixed with ‘*’. If no ‘*’ is specified, as
always chooses PC relative addressing for jump/call labels.
Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, long, or quadruple) with an instruction mnemonic suffix (‘b’, ‘w’, ‘l’ or ‘q’, respectively).
The x86-64 architecture adds an RIP (instruction pointer relative) addressing. This addressing mode is specified by using ‘rip’ as a base register. Only constant offsets are valid. For example:
symbol
in RIP relative way, this is shorter than
the default absolute addressing.
Other addressing modes remain unchanged in x86-64 architecture, except registers used are 64-bit instead of 32-bit.
Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long displacement is used. We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the ‘data16’ instruction prefix), since the 80386 insists upon masking ‘%eip’ to 16 bits after the word displacement is added. (See also see i386-Arch)
Note that the ‘jcxz’, ‘jecxz’, ‘loop’, ‘loopz’,
‘loope’, ‘loopnz’ and ‘loopne’ instructions only come in byte
displacements, so that if you use these instructions (gcc
does
not use them) you may get an error message (and incorrect code). The AT&T
80386 assembler tries to get around this problem by expanding ‘jcxz foo’
to
jcxz cx_zero jmp cx_nonzero cx_zero: jmp foo cx_nonzero:
All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an instruction mnemonic suffix and a constructor associated with it. Instruction mnemonic suffixes specify the operand's data type. Constructors build these data types into memory.
Register to register operations should not use instruction mnemonic suffixes. ‘fstl %st, %st(1)’ will give a warning, and be assembled as if you wrote ‘fst %st, %st(1)’, since all register to register operations use 80-bit floating point operands. (Contrast this with ‘fstl %st, mem’, which converts ‘%st’ from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location ‘mem’)
as
supports Intel's MMX instruction set (SIMD
instructions for integer data), available on Intel's Pentium MMX
processors and Pentium II processors, AMD's K6 and K6-2 processors,
Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!
instruction set (SIMD instructions for 32-bit floating point data)
available on AMD's K6-2 processor and possibly others in the future.
Currently, as
does not support Intel's floating point
SIMD, Katmai (KNI).
The eight 64-bit MMX operands, also used by 3DNow!, are called ‘%mm0’, ‘%mm1’, ... ‘%mm7’. They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values. The MMX registers cannot be used at the same time as the floating point stack.
See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.
as
supports AMD's Lightweight Profiling (LWP)
instruction set, available on AMD's Family 15h (Orochi) processors.
LWP enables applications to collect and manage performance data, and react to performance events. The collection of performance data requires no context switches. LWP runs in the context of a thread and so several counters can be used independently across multiple threads. LWP can be used in both 64-bit and legacy 32-bit modes.
For detailed information on the LWP instruction set, see the AMD Lightweight Profiling Specification available at Lightweight Profiling Specification.
as
supports the Bit Manipulation (BMI) instruction set.
BMI instructions provide several instructions implementing individual bit manipulation operations such as isolation, masking, setting, or resetting.
as
supports AMD's Trailing Bit Manipulation (TBM)
instruction set, available on AMD's BDVER2 processors (Trinity and
Viperfish).
TBM instructions provide instructions implementing individual bit manipulation operations such as isolating, masking, setting, resetting, complementing, and operations on trailing zeros and ones.
While as
normally writes only “pure” 32-bit i386 code
or 64-bit x86-64 code depending on the default configuration,
it also supports writing code to run in real mode or in 16-bit protected
mode code segments. To do this, put a ‘.code16’ or
‘.code16gcc’ directive before the assembly language instructions to
be run in 16-bit mode. You can switch as
to writing
32-bit code with the ‘.code32’ directive or 64-bit code with the
‘.code64’ directive.
‘.code16gcc’ provides experimental support for generating 16-bit code from gcc, and differs from ‘.code16’ in that ‘call’, ‘ret’, ‘enter’, ‘leave’, ‘push’, ‘pop’, ‘pusha’, ‘popa’, ‘pushf’, and ‘popf’ instructions default to 32-bit size. This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. ‘.code16gcc’ also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates.
The code which as
generates in 16-bit mode will not
necessarily run on a 16-bit pre-80386 processor. To write code that
runs on such a processor, you must refrain from using any 32-bit
constructs which require as
to output address or operand
size prefixes.
Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code generates the machine opcode bytes ‘66 6a 04’, which pushes the value ‘4’ onto the stack, decrementing ‘%esp’ by 2.
pushw $4
The same code in a 16-bit code section would generate the machine opcode bytes ‘6a 04’ (i.e., without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section.
as
may be told to assemble for a particular CPU
(sub-)architecture with the .arch
cpu_type directive. This
directive enables a warning when gas detects an instruction that is not
supported on the CPU specified. The choices for cpu_type are:
‘i8086’ | ‘i186’ | ‘i286’ | ‘i386’
|
‘i486’ | ‘i586’ | ‘i686’ | ‘pentium’
|
‘pentiumpro’ | ‘pentiumii’ | ‘pentiumiii’ | ‘pentium4’
|
‘prescott’ | ‘nocona’ | ‘core’ | ‘core2’
|
‘corei7’ | ‘l1om’ | ‘k1om’ | ‘iamcu’
|
‘k6’ | ‘k6_2’ | ‘athlon’ | ‘k8’
|
‘amdfam10’ | ‘bdver1’ | ‘bdver2’ | ‘bdver3’
|
‘bdver4’ | ‘znver1’ | ‘znver2’ | ‘btver1’
|
‘btver2’ | ‘generic32’ | ‘generic64’
| |
‘.cmov’ | ‘.fxsr’ | ‘.mmx’
| |
‘.sse’ | ‘.sse2’ | ‘.sse3’
| |
‘.ssse3’ | ‘.sse4.1’ | ‘.sse4.2’ | ‘.sse4’
|
‘.avx’ | ‘.vmx’ | ‘.smx’ | ‘.ept’
|
‘.clflush’ | ‘.movbe’ | ‘.xsave’ | ‘.xsaveopt’
|
‘.aes’ | ‘.pclmul’ | ‘.fma’ | ‘.fsgsbase’
|
‘.rdrnd’ | ‘.f16c’ | ‘.avx2’ | ‘.bmi2’
|
‘.lzcnt’ | ‘.invpcid’ | ‘.vmfunc’ | ‘.hle’
|
‘.rtm’ | ‘.adx’ | ‘.rdseed’ | ‘.prfchw’
|
‘.smap’ | ‘.mpx’ | ‘.sha’ | ‘.prefetchwt1’
|
‘.clflushopt’ | ‘.xsavec’ | ‘.xsaves’ | ‘.se1’
|
‘.avx512f’ | ‘.avx512cd’ | ‘.avx512er’ | ‘.avx512pf’
|
‘.avx512vl’ | ‘.avx512bw’ | ‘.avx512dq’ | ‘.avx512ifma’
|
‘.avx512vbmi’ | ‘.avx512_4fmaps’ | ‘.avx512_4vnniw’
| |
‘.avx512_vpopcntdq’ | ‘.avx512_vbmi2’ | ‘.avx512_vnni’
| |
‘.avx512_bitalg’ | ‘.avx512_bf16’ | ‘.avx512_vp2intersect’
| |
‘.clwb’ | ‘.rdpid’ | ‘.ptwrite’ | |
‘.ibt’
| |||
‘.wbnoinvd’ | ‘.pconfig’ | ‘.waitpkg’ | ‘.cldemote’
|
‘.shstk’ | ‘.gfni’ | ‘.vaes’ | ‘.vpclmulqdq’
|
‘.movdiri’ | ‘.movdir64b’ | ‘.enqcmd’
| |
‘.3dnow’ | ‘.3dnowa’ | ‘.sse4a’ | ‘.sse5’
|
‘.syscall’ | ‘.rdtscp’ | ‘.svme’ | ‘.abm’
|
‘.lwp’ | ‘.fma4’ | ‘.xop’ | ‘.cx16’
|
‘.padlock’ | ‘.clzero’ | ‘.mwaitx’ | ‘.rdpru’
|
‘.mcommit’
|
Apart from the warning, there are only two other effects on
as
operation; Firstly, if you specify a CPU other than
‘i486’, then shift by one instructions such as ‘sarl $1, %eax’
will automatically use a two byte opcode sequence. The larger three
byte opcode sequence is used on the 486 (and when no architecture is
specified) because it executes faster on the 486. Note that you can
explicitly request the two byte opcode by writing ‘sarl %eax’.
Secondly, if you specify ‘i8086’, ‘i186’, or ‘i286’,
and ‘.code16’ or ‘.code16gcc’ then byte offset
conditional jumps will be promoted when necessary to a two instruction
sequence consisting of a conditional jump of the opposite sense around
an unconditional jump to the target.
Following the CPU architecture (but not a sub-architecture, which are those
starting with a dot), you may specify ‘jumps’ or ‘nojumps’ to
control automatic promotion of conditional jumps. ‘jumps’ is the
default, and enables jump promotion; All external jumps will be of the long
variety, and file-local jumps will be promoted as necessary.
(see i386-Jumps) ‘nojumps’ leaves external conditional jumps as
byte offset jumps, and warns about file-local conditional jumps that
as
promotes.
Unconditional jumps are treated as for ‘jumps’.
For example
.arch i8086,nojumps
The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.
For example
fsub %st,%st(3)
results in ‘%st(3)’ being updated to ‘%st - %st(3)’ rather than the expected ‘%st(3) - %st’. This happens with all the non-commutative arithmetic floating point operations with two register operands where the source register is ‘%st’ and the destination register is ‘%st(i)’.
There is some trickery concerning the ‘mul’ and ‘imul’
instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
multiplies (base opcode ‘0xf6’; extension 4 for ‘mul’ and 5
for ‘imul’) can be output only in the one operand form. Thus,
‘imul %ebx, %eax’ does not select the expanding multiply;
the expanding multiply would clobber the ‘%edx’ register, and this
would confuse gcc
output. Use ‘imul %ebx’ to get the
64-bit product in ‘%edx:%eax’.
We have added a two operand form of ‘imul’ when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying ‘%eax’ by 69, for example, can be done with ‘imul $69, %eax’ rather than ‘imul $69, %eax, %eax’.
-mlp64
(LP64 data model).
-mle
option selects little-endian
byte order (default) and -mbe
selects big-endian byte order. Note that
IA-64 machine code always uses little-endian byte order.
-munwind-check=warning
will make the assembler issue a warning when an unwind directive check
fails. This is the default. -munwind-check=error
will make the
assembler issue an error when an unwind directive check fails.
-mhint.b=ok
will make the assembler accept
‘hint.b’. -mint.b=warning
will make the assembler issue a
warning when ‘hint.b’ is used. -mhint.b=error
will make
the assembler treat ‘hint.b’ as an error, which is the default.
The assembler syntax closely follows the IA-64 Assembly Language Reference Guide.
‘//’ is the line comment token.
‘;’ can be used instead of a newline to separate statements.
The 128 integer registers are referred to as ‘rn’. The 128 floating-point registers are referred to as ‘fn’. The 128 application registers are referred to as ‘arn’. The 128 control registers are referred to as ‘crn’. The 64 one-bit predicate registers are referred to as ‘pn’. The 8 branch registers are referred to as ‘bn’. In addition, the assembler defines a number of aliases: ‘gp’ (‘r1’), ‘sp’ (‘r12’), ‘rp’ (‘b0’), ‘ret0’ (‘r8’), ‘ret1’ (‘r9’), ‘ret2’ (‘r10’), ‘ret3’ (‘r9’), ‘fargn’ (‘f8+n’), and ‘fretn’ (‘f8+n’).
For convenience, the assembler also defines aliases for all named application and control registers. For example, ‘ar.bsp’ refers to the register backing store pointer (‘ar17’). Similarly, ‘cr.eoi’ refers to the end-of-interrupt register (‘cr67’).
The assembler defines bit masks for each of the bits in the IA-64 processor status register. For example, ‘psr.ic’ corresponds to a value of 0x2000. These masks are primarily intended for use with the ‘ssm’/‘sum’ and ‘rsm’/‘rum’ instructions, but they can be used anywhere else where an integer constant is expected.
In addition to the standard IA-64 relocations, the following relocations are
implemented by as
:
@slotcount(
V)
For detailed information on the IA-64 machine instruction set, see the IA-64 Architecture Handbook.
The Ubicom IP2K version of as
has a few machine
dependent options:
-mip2022ext
as
can assemble the extended IP2022 instructions, but
it will only do so if this is specifically allowed via this command
line option.
-mip2022
The presence of a ‘;’ on a line indicates the start of a comment that extends to the end of the current line.
If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The IP2K assembler does not currently support a line separator character.
-mmultiply-enabled
-mdivide-enabled
-mbarrel-shift-enabled
-msign-extend-enabled
-muser-enabled
-micache-enabled
-mdcache-enabled
-mbreak-enabled
-mall-enabled
LM32 has 32 x 32-bit general purpose registers ‘r0’, ‘r1’, ... ‘r31’.
The following aliases are defined: ‘gp’ - ‘r26’, ‘fp’ - ‘r27’, ‘sp’ - ‘r28’, ‘ra’ - ‘r29’, ‘ea’ - ‘r30’, ‘ba’ - ‘r31’.
LM32 has the following Control and Status Registers (CSRs).
IE
IM
IP
ICC
DCC
CC
CFG
EBA
DC
DEBA
JTX
JRX
BP0
BP1
BP2
BP3
WP0
WP1
WP2
WP3
The assembler supports several modifiers when using relocatable addresses in LM32 instruction operands. The general syntax is the following:
modifier(relocatable-expression)
lo
hi
For example
ori r4, r4, lo(sym+10) orhi r4, r4, hi(sym+10)
gp
mva r4, gp(sym)
got
lw r4, (gp+got(sym))
gotofflo16
gotoffhi16
orhi r4, r4, gotoffhi16(lsym) addi r4, r4, gotofflo16(lsym)
The presence of a ‘#’ on a line indicates the start of a comment that extends to the end of the current line. Note that if a line starts with a ‘#’ character then it can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
A semicolon (‘;’) can be used to separate multiple statements on the same line.
For detailed information on the LM32 machine instruction set, see http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/.
as
implements all the standard LM32 opcodes.
as
can assemble code for several different members of
the Renesas M32C family. Normally the default is to assemble code for
the M16C microprocessor. The -m32c
option may be used to
change the default to the M32C microprocessor.
The Renesas M32C version of as
has these
machine-dependent options:
-m32c
-m16c
-relax
-h-tick-hex
The assembler supports several modifiers when using symbol addresses in M32C instruction operands. The general syntax is the following:
%modifier(symbol)
%dsp8
%dsp16
mov.w %dsp8(sym)[a0],r1 mov.b #0,%dsp8(sym)[a0]
%hi8
mov.b #%hi8(sym),r1h mov.w #%lo16(sym),a0 smovf.b
%lo16
%hi16
mov.w #%hi16(sym),a1 mov.w #%lo16(sym),a0 ... lde.w [a1a0],r1
The presence of a ‘;’ character on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘|’ character can be used to separate statements on the same line.
The Renesas M32R version of as
has a few machine
dependent options:
-m32rx
as
can assemble code for several different members of the
Renesas M32R family. Normally the default is to assemble code for
the M32R microprocessor. This option may be used to change the default
to the M32RX microprocessor, which adds some more instructions to the
basic M32R instruction set, and some additional parameters to some of
the original instructions.
-m32r2
-m32r
-little
-EL
-big
-EB
-KPIC
-parallel
-no-parallel
-no-bitinst
-O
-warn-explicit-parallel-conflicts
as
to produce warning messages when
questionable parallel instructions are encountered. This option is
enabled by default, but gcc
disables it when it invokes
as
directly. Questionable instructions are those whose
behaviour would be different if they were executed sequentially. For
example the code fragment ‘mv r1, r2 || mv r3, r1’ produces a
different result from ‘mv r1, r2 \n mv r3, r1’ since the former
moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
and r3.
-Wp
-no-warn-explicit-parallel-conflicts
as
not to produce warning messages when
questionable parallel instructions are encountered.
-Wnp
-ignore-parallel-conflicts
-no-ignore-parallel-conflicts
-Ip
-nIp
-warn-unmatched-high
.high
pseudo op is encountered without a matching .low
pseudo op. The presence of such an unmatched pseudo op usually
indicates a programming error.
-no-warn-unmatched-high
-Wuh
-Wnuh
The Renesas M32R version of as
has a few architecture
specific directives:
low
expressionlow
directive computes the value of its expression and
places the lower 16-bits of the result into the immediate-field of the
instruction. For example:
or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
high
expressionhigh
directive computes the value of its expression and
places the upper 16-bits of the result into the immediate-field of the
instruction. For example:
seth r0, #high(0x12345678) ; compute r0 = 0x12340000 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
shigh
expressionshigh
directive is very similar to the high
directive. It also computes the value of its expression and places
the upper 16-bits of the result into the immediate-field of the
instruction. The difference is that shigh
also checks to see
if the lower 16-bits could be interpreted as a signed number, and if
so it assumes that a borrow will occur from the upper-16 bits. To
compensate for this the shigh
directive pre-biases the upper
16 bit value by adding one to it. For example:
For example:
seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000
In the second example the lower 16-bits are 0x8000. If these are treated as a signed value and sign extended to 32-bits then the value becomes 0xffff8000. If this value is then added to 0x00010000 then the result is 0x00008000.
This behaviour is to allow for the different semantics of the
or3
and add3
instructions. The or3
instruction
treats its 16-bit immediate argument as unsigned whereas the
add3
treats its 16-bit immediate as a signed value. So for
example:
seth r0, #shigh(0x00008000) add3 r0, r0, #low(0x00008000)
Produces the correct result in r0, whereas:
seth r0, #shigh(0x00008000) or3 r0, r0, #low(0x00008000)
Stores 0xffff8000 into r0.
Note - the shigh
directive does not know where in the assembly
source code the lower 16-bits of the value are going set, so it cannot
check to make sure that an or3
instruction is being used rather
than an add3
instruction. It is up to the programmer to make
sure that correct directives are used.
.m32r
.m32rx
.m32r2
.little
.big
There are several warning and error messages that can be produced by
as
which are specific to the M32R:
output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
instruction ‘
...’ is for the M32RX only
unknown instruction ‘
...’
only the NOP instruction can be issued in parallel on the m32r
instruction ‘
...’ cannot be executed in parallel.
Instructions share the same execution pipeline
Instructions write to the same destination register.
The Motorola 680x0 version of as
has a few machine
dependent options:
68000
,
68010
,
68020
,
68030
,
68040
,
68060
,
cpu32
,
isaa
,
isaaplus
,
isab
,
isac
and
cfv4e
.
long
(32 bits). (Since
as
cannot know where these symbols end up, as
can
only allocate space for the linker to fill in later. Since as
does not know how far away these symbols are, it allocates as much space as it
can.) If you use this option, the references are only one word wide (16 bits).
This may be useful if you want the object file to be as small as possible, and
you know that the relevant symbols are always less than 17 bits away.
as
will normally use the full 32 bit value.
For example, the addressing mode ‘%a0@(%d0)’ is equivalent to
‘%a0@(%d0:l)’. You may use the ‘--base-size-default-16’
option to tell as
to default to using the 16 bit value.
In this case, ‘%a0@(%d0)’ is equivalent to ‘%a0@(%d0:w)’.
You may use the ‘--base-size-default-32’ option to restore the
default behaviour.
as
will normally assume that
the value is 32 bits. For example, if the symbol ‘disp’ has not
been defined, as
will assemble the addressing mode
‘%a0@(disp,%d0)’ as though ‘disp’ is a 32 bit value. You may
use the ‘--disp-size-default-16’ option to tell as
to instead assume that the displacement is 16 bits. In this case,
as
will assemble ‘%a0@(disp,%d0)’ as though
‘disp’ is a 16 bit value. You may use the
‘--disp-size-default-32’ option to restore the default behaviour.
as
needs a long branch
that is not available, it normally emits an absolute jump instead. This
option disables this substitution. When this option is given and no long
branches are available, only word branches will be emitted. An error
message will be generated if a word branch cannot reach its target. This
option has no effect on 68020 and other processors that have long branches.
see Branch Improvement.
as
can assemble code for several different members of the
Motorola 680x0 family. The default depends upon how as
was configured when it was built; normally, the default is to assemble
code for the 68020 microprocessor. The following options may be used to
change the default. These options control which instructions and
addressing modes are permitted. The members of the 680x0 family are
very similar. For detailed information about the differences, see the
Motorola manuals.
This syntax for the Motorola 680x0 was developed at mit.
The 680x0 version of as
uses instructions names and
syntax compatible with the Sun assembler. Intervening periods are
ignored; for example, ‘movl’ is equivalent to ‘mov.l’.
In the following table apc stands for any of the address registers (‘%a0’ through ‘%a7’), the program counter (‘%pc’), the zero-address relative to the program counter (‘%zpc’), a suppressed address register (‘%za0’ through ‘%za7’), or it may be omitted entirely. The use of size means one of ‘w’ or ‘l’, and it may be omitted, along with the leading colon, unless a scale is also specified. The use of scale means one of ‘1’, ‘2’, ‘4’, or ‘8’, and it may always be omitted along with the leading colon.
The following addressing modes are understood:
%a6
is also known as ‘%fp’, the Frame Pointer.
The number may be omitted.
The onumber or the register, but not both, may be omitted.
The number may be omitted. Omitting the register produces
the Postindex addressing mode.
The standard Motorola syntax for this chip differs from the syntax
already discussed (see Syntax). as
can
accept Motorola syntax for operands, even if mit syntax is used for
other operands in the same instruction. The two kinds of syntax are
fully compatible.
In the following table apc stands for any of the address registers (‘%a0’ through ‘%a7’), the program counter (‘%pc’), the zero-address relative to the program counter (‘%zpc’), or a suppressed address register (‘%za0’ through ‘%za7’). The use of size means one of ‘w’ or ‘l’, and it may always be omitted along with the leading dot. The use of scale means one of ‘1’, ‘2’, ‘4’, or ‘8’, and it may always be omitted along with the leading asterisk.
The following additional addressing modes are understood:
%a6
is also known as ‘%fp’, the Frame Pointer.
The number may also appear within the parentheses, as in
‘(number,%a0)’. When used with the pc, the
number may be omitted (with an address register, omitting the
number produces Address Register Indirect mode).
The number may be omitted, or it may appear within the
parentheses. The apc may be omitted. The register and the
apc may appear in either order. If both apc and
register are address registers, and the size and scale
are omitted, then the first register is taken as the base register, and
the second as the index register.
The onumber, or the register, or both, may be omitted.
Either the number or the apc may be omitted, but not both.
The number, or the apc, or the register, or any two of them, may be omitted. The onumber may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.
Packed decimal (P) format floating literals are not supported. Feel free to add the code!
The floating point formats generated by directives are these.
.float
Single
precision floating point constants.
.double
Double
precision floating point constants.
.extend
.ldouble
Extended
precision (long double
) floating point constants.
In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives.
.data1
.data 1
directive.
.data2
.data 2
directive.
.even
.align
directive; it
aligns the output to an even byte boundary.
.skip
.space
directive.
.arch
name.cpu
nameCertain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting ‘j’ for ‘b’ at the start of a Motorola mnemonic.
The following table summarizes the pseudo-operations. A *
flags
cases that are more fully described after the table:
Displacement +------------------------------------------------------------ | 68020 68000/10, not PC-relative OK Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** +------------------------------------------------------------ jbsr |bsrs bsrw bsrl jsr jra |bras braw bral jmp * jXX |bXXs bXXw bXXl bNXs;jmp * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp fjXX | N/A fbXXw fbXXl N/A XX: condition NX: negative of condition XX
*
—see full description below**
—this expansion mode is disallowed by ‘--pcrel’jbsr
jra
In addition to standard branch operands, as
allows these
pseudo-operations to have all operands that are allowed for jsr and jmp,
substituting these instructions if the operand given is not valid for a
branch instruction.
j
XXjhi jls jcc jcs jne jeq jvc jvs jpl jmi jge jlt jgt jle
Usually, each of these pseudo-operations expands to a single branch
instruction. However, if a word branch is not sufficient, no long branches
are available, and the ‘--pcrel’ option is not given, as
issues a longer code fragment in terms of NX, the opposite condition
to XX. For example, under these conditions:
jXX foo
gives
bNXs oof jmp foo oof:
db
XXdbhi dbls dbcc dbcs dbne dbeq dbvc dbvs dbpl dbmi dbge dblt dbgt dble dbf dbra dbt
Motorola ‘dbXX’ instructions allow word displacements only. When
a word displacement is sufficient, each of these pseudo-operations expands
to the corresponding Motorola instruction. When a word displacement is not
sufficient and long branches are available, when the source reads
‘dbXX foo’, as
emits
dbXX oo1 bras oo2 oo1:bral foo oo2:
If, however, long branches are not available and the ‘--pcrel’ option is
not given, as
emits
dbXX oo1 bras oo2 oo1:jmp foo oo2:
fj
XXfjne fjeq fjge fjlt fjgt fjle fjf fjt fjgl fjgle fjnge fjngl fjngle fjngt fjnle fjnlt fjoge fjogl fjogt fjole fjolt fjor fjseq fjsf fjsne fjst fjueq fjuge fjugt fjule fjult fjun
Each of these pseudo-operations always expands to a single Motorola coprocessor branch instruction, word or long. All Motorola coprocessor branch instructions allow both word and long displacements.
Line comments are introduced by the ‘|’ character appearing anywhere on a line, unless the --bitwise-or command-line option has been specified.
An asterisk (‘*’) as the first character on a line marks the start of a line comment as well.
A hash character (‘#’) as the first character on a line also marks the start of a line comment, but in this case it could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing). If the hash character appears elsewhere on a line it is used to introduce an immediate value. (This is for compatibility with Sun's assembler).
Multiple statements on the same line can appear if they are separated by the ‘;’ character.
The Motorola 68HC11 and 68HC12 version of as
have a few machine
dependent options.
-m68hc11
-m68hc12
-m68hcs12
-mm9s12x
-mm9s12xg
--xgate-ramoffset
-mshort
-mlong
-mshort-double
-mlong-double
--strict-direct-mode
as
will ignore it and generate an absolute addressing.
This option prevents as
from doing this, and the wrong
usage of the direct page mode will raise an error.
--short-branches
as
transforms the relative
branch (‘bsr’, ‘bgt’, ‘bge’, ‘beq’, ‘bne’,
‘ble’, ‘blt’, ‘bhi’, ‘bcc’, ‘bls’,
‘bcs’, ‘bmi’, ‘bvs’, ‘bvs’, ‘bra’) into
an absolute branch when the offset is out of the -128 .. 127 range.
In that case, the ‘bsr’ instruction is translated into a
‘jsr’, the ‘bra’ instruction is translated into a
‘jmp’ and the conditional branches instructions are inverted and
followed by a ‘jmp’. This option disables these translations
and as
will generate an error if a relative branch
is out of range. This option does not affect the optimization
associated to the ‘jbra’, ‘jbsr’ and ‘jbXX’ pseudo opcodes.
--force-long-branches
--print-insn-syntax
--print-opcodes
as
exits.
--generate-example
In the M68HC11 syntax, the instruction name comes first and it may
be followed by one or several operands (up to three). Operands are
separated by comma (‘,’). In the normal mode,
as
will complain if too many operands are specified for
a given instruction. In the MRI mode (turned on with ‘-M’ option),
it will treat them as comments. Example:
inx lda #23 bset 2,x #4 brclr *bot #8 foo
The presence of a ‘;’ character or a ‘!’ character anywhere on a line indicates the start of a comment that extends to the end of that line.
A ‘*’ or a ‘#’ character at the start of a line also introduces a line comment, but these characters do not work elsewhere on the line. If the first character of the line is a ‘#’ then as well as starting a comment, the line could also be logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The M68HC11 assembler does not currently support a line separator character.
The following addressing modes are understood for 68HC11 and 68HC12:
The number may be omitted in which case 0 is assumed.
The M68HC12 has other more complex addressing modes. All of them are supported and they are represented below:
The number may be omitted in which case 0 is assumed.
The register can be either ‘X’, ‘Y’, ‘SP’ or
‘PC’. The assembler will use the smaller post-byte definition
according to the constant value (5-bit constant offset, 9-bit constant
offset or 16-bit constant offset). If the constant is not known by
the assembler it will use the 16-bit constant offset post-byte and the value
will be resolved at link time.
The register can be either ‘X’, ‘Y’, ‘SP’ or ‘PC’.
The number must be in the range ‘-8’..‘+8’ and must not be 0.
The register can be either ‘X’, ‘Y’, ‘SP’ or ‘PC’.
The accumulator register can be either ‘A’, ‘B’ or ‘D’.
The register can be either ‘X’, ‘Y’, ‘SP’ or ‘PC’.
The register can be either ‘X’, ‘Y’, ‘SP’ or ‘PC’.
For example:
ldab 1024,sp ldd [10,x] orab 3,+x stab -2,y- ldx a,pc sty [d,sp]
The assembler supports several modifiers when using symbol addresses in 68HC11 and 68HC12 instruction operands. The general syntax is the following:
%modifier(symbol)
%addr
%page
%hi
%lo
For example a 68HC12 call to a function ‘foo_example’ stored in memory expansion part could be written as follows:
call %addr(foo_example),%page(foo_example)
and this is equivalent to
call foo_example
And for 68HC11 it could be written as follows:
ldab #%page(foo_example) stab _page_switch jsr %addr(foo_example)
The 68HC11 and 68HC12 version of as
have the following
specific assembler directives:
.relax
.mode [mshort|mlong|mshort-double|mlong-double]
.far
symbol.interrupt
symbol.xrefb
symbolPacked decimal (P) format floating literals are not supported. Feel free to add the code!
The floating point formats generated by directives are these.
.float
Single
precision floating point constants.
.double
Double
precision floating point constants.
.extend
.ldouble
Extended
precision (long double
) floating point constants.
Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by prepending ‘j’ to the start of Motorola mnemonic. These pseudo opcodes are not affected by the ‘--short-branches’ or ‘--force-long-branches’ options.
The following table summarizes the pseudo-operations.
Displacement Width +-------------------------------------------------------------+ | Options | | --short-branches --force-long-branches | +--------------------------+----------------------------------+ Op |BYTE WORD | BYTE WORD | +--------------------------+----------------------------------+ bsr | bsr <pc-rel> <error> | jsr <abs> | bra | bra <pc-rel> <error> | jmp <abs> | jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | | jmp <abs> | | +--------------------------+----------------------------------+ XX: condition NX: negative of condition XX
jbsr
jbra
jb
XXjbcc jbeq jbge jbgt jbhi jbvs jbpl jblo jbcs jbne jblt jble jbls jbvc jbmi
For the cases of non-PC relative displacements and long displacements,
as
issues a longer code fragment in terms of
NX, the opposite condition to XX. For example, for the
non-PC relative case:
jbXX foo
gives
bNXs oof jmp foo oof:
The Xilinx MicroBlaze processor family includes several variants, all using the same core instruction set. This chapter covers features of the gnu assembler that are specific to the MicroBlaze architecture. For details about the MicroBlaze instruction set, please see the MicroBlaze Processor Reference Guide (UG081) available at www.xilinx.com.
A number of assembler directives are available for MicroBlaze.
.data8
expression,...
.byte
. Each expression is assembled
into an eight-bit value.
.data16
expression,...
.hword
. Each expression is assembled
into an 16-bit value.
.data32
expression,...
.word
. Each expression is assembled
into an 32-bit value.
.ent
name[,
label]
.func
denoting the start of function
name at (optional) label.
.end
name[,
label]
.endfunc
denoting the end of function
name.
.gpword
label,...
.rva
. The resolved address of label
is stored in the data section.
.weakext
label.rodata
.section .rodata
.sdata2
.section .sdata2
.sdata
.section .sdata
.bss
.section .bss
.sbss
.section .sbss
The presence of a ‘#’ on a line indicates the start of a comment that extends to the end of the current line.
If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘;’ character can be used to separate statements on the same line.
gnu as
for MIPS architectures supports several
different MIPS processors, and MIPS ISA levels I through V, MIPS32,
and MIPS64. For information about the MIPS instruction set, see
MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall).
For an overview of MIPS assembly conventions, see “Appendix D:
Assembly Language Programming” in the same work.
The MIPS configurations of gnu as
support these
special options:
-G
num-EB
-EL
as
can select big-endian or
little-endian output at run time (unlike the other gnu development
tools, which must be configured for one or the other). Use ‘-EB’
to select big-endian output, and ‘-EL’ for little-endian.
-KPIC
-mvxworks-pic
-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips32r3
-mips32r5
-mips32r6
-mips64
-mips64r2
-mips64r3
-mips64r5
-mips64r6
-mgp32
-mfp32
The .set gp=32
and .set fp=32
directives allow the size
of registers to be changed for parts of an object. The default value is
restored by .set gp=default
and .set fp=default
.
On some MIPS variants there is a 32-bit mode flag; when this flag is
set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
save the 32-bit registers on a context switch, so it is essential never
to use the 64-bit registers.
-mgp64
-mfp64
The .set gp=64
and .set fp=64
directives allow the size
of registers to be changed for parts of an object. The default value is
restored by .set gp=default
and .set fp=default
.
-mfpxx
The .set fp=xx
directive allows a part of an object to be marked
as not making assumptions about 32-bit or 64-bit FP registers. The
default value is restored by .set fp=default
.
-modd-spreg
-mno-odd-spreg
-mips16
-no-mips16
.module mips16
at the start of the assembly file. ‘-no-mips16’
turns off this option.
-mmips16e2
-mno-mips16e2
.module mips16e2
at the start of the assembly file.
‘-mno-mips16e2’ turns off this option.
-mmicromips
-mno-micromips
.module micromips
at the start of the assembly file.
‘-mno-micromips’ turns off this option. This is equivalent to putting
.module nomicromips
at the start of the assembly file.
-msmartmips
-mno-smartmips
.module smartmips
at the start of the assembly file.
‘-mno-smartmips’ turns off this option.
-mips3d
-no-mips3d
-mdmx
-no-mdmx
-mdsp
-mno-dsp
-mdspr2
-mno-dspr2
-mdspr3
-mno-dspr3
-mmt
-mno-mt
-mmcu
-mno-mcu
-mmsa
-mno-msa
-mxpa
-mno-xpa
-mvirt
-mno-virt
-mcrc
-mno-crc
-mginv
-mno-ginv
-mloongson-mmi
-mno-loongson-mmi
-mloongson-cam
-mno-loongson-cam
-mloongson-ext
-mno-loongson-ext
-mloongson-ext2
-mno-loongson-ext2
-minsn32
-mno-insn32
.set insn32
at
the start of the assembly file. ‘-mno-insn32’ turns off this
option. This is equivalent to putting .set noinsn32
at the
start of the assembly file. By default ‘-mno-insn32’ is
selected, allowing all instructions to be used.
-mfix7000
-mno-fix7000
-mfix-rm7000
-mno-fix-rm7000
-mfix-loongson2f-jump
-mno-fix-loongson2f-jump
-mfix-loongson2f-nop
-mno-fix-loongson2f-nop
or at,at,zero
to work around the Loongson2F
‘nop’ errata. Without it, under extreme cases, the CPU might
deadlock. The issue has been solved in later Loongson2F batches, but
this fix has no side effect to them.
-mfix-loongson3-llsc
-mno-fix-loongson3-llsc
-mfix-vr4120
-mno-fix-vr4120
-mfix-vr4130
-mno-fix-vr4130
-mfix-24k
-mno-fix-24k
-mfix-cn63xxp1
-mno-fix-cn63xxp1
pref
hints 0 - 4 and 6 - 24 with hint 28 to work around
certain CN63XXP1 errata.
-mfix-r5900
-mno-fix-r5900
nop
instruction there
instead. The short loop bug under certain conditions causes loops to
execute only once or twice, due to a hardware bug in the R5900 chip.
-m4010
-no-m4010
-m4650
-no-m4650
-m3900
-no-m3900
-m4100
-no-m4100
-march=
cpu2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, interaptiv, interaptiv-mr2, m5100, m5101, p5600, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, i6400, i6500, p6600, loongson2e, loongson2f, gs464, gs464e, gs264e, octeon, octeon+, octeon2, octeon3, xlr, xlp
For compatibility reasons, ‘nx’ and ‘bfx’ are
accepted as synonyms for ‘nf1_1’. These values are
deprecated.
-mtune=
cpu-mabi=
abi-msym32
-mno-sym32
.set sym32
or .set nosym32
to
the beginning of the assembler input. See MIPS Symbol Sizes.
-nocpp
as
, there is no need for ‘-nocpp’, because the
gnu assembler itself never runs the C preprocessor.
-msoft-float
-mhard-float
-msingle-float
-mdouble-float
--construct-floats
--no-construct-floats
--no-construct-floats
option disables the construction of
double width floating point constants by loading the two halves of the
value into the two single width floating point registers that make up
the double width register. This feature is useful if the processor
support the FR bit in its status register, and this bit is known (by
the programmer) to be set. This bit prevents the aliasing of the double
width register by the single width registers.
By default --construct-floats
is selected, allowing construction
of these floating point constants.
--relax-branch
--no-relax-branch
The BC1ANY2F
, BC1ANY2T
, BC1ANY4F
, BC1ANY4T
,
BPOSGE32
and BPOSGE64
instructions are excluded from
relaxation, because they have no complementing counterparts. They could
be relaxed with the use of a longer sequence involving another branch,
however this has not been implemented and if their target turns out of
reach, they produce an error even if branch relaxation is enabled.
Also no MIPS16 branches are ever relaxed.
By default ‘--no-relax-branch’ is selected, causing any out-of-range
branches to produce an error.
-mignore-branch-isa
-mno-ignore-branch-isa
The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. If the ISA modes do not match, then such a branch, if taken, will cause the ISA mode to remain unchanged and instructions that follow will be executed in the wrong ISA mode causing the program to misbehave or crash.
In the case of the BAL
instruction it may be possible to relax
it to an equivalent JALX
instruction so that the ISA mode is
switched at the run time as required. For other branches no relaxation
is possible and therefore GAS has checks implemented that verify in
branch assembly that the two ISA modes match, and report an error
otherwise so that the problem with code can be diagnosed at the assembly
time rather than at the run time.
However some assembly code, including generated code produced by some versions of GCC, may incorrectly include branches to data labels, which appear to require a mode switch but are either dead or immediately followed by valid instructions encoded for the same ISA the branch has been encoded for. While not strictly correct at the source level such code will execute as intended, so to help with these cases ‘-mignore-branch-isa’ is supported which disables ISA mode checks for branches.
By default ‘-mno-ignore-branch-isa’ is selected, causing any invalid branch requiring a transition between ISA modes to produce an error.
-mnan=
encoding.nan
directive to the beginning of the source file. See MIPS NaN Encodings.
-mnan=legacy is the default if no -mnan option or
.nan
directive is used.
--trap
--no-break
as
automatically macro expands certain division and
multiplication instructions to check for overflow and division by zero. This
option causes as
to generate code to take a trap exception
rather than a break exception when an error is detected. The trap instructions
are only supported at Instruction Set Architecture level 2 and higher.
--break
--no-trap
-mpdr
-mno-pdr
.pdr
sections. Off by default on IRIX, on
elsewhere.
-mshared
-mno-shared
MIPS assemblers have traditionally provided a wider range of instructions than the MIPS architecture itself. These extra instructions are usually referred to as “macro” instructions 2.
Some MIPS macro instructions extend an underlying architectural instruction
while others are entirely new. An example of the former type is and
,
which allows the third operand to be either a register or an arbitrary
immediate value. Examples of the latter type include bgt
, which
branches to the third operand when the first operand is greater than
the second operand, and ulh
, which implements an unaligned
2-byte load.
One of the most common extensions provided by macros is to expand
memory offsets to the full address range (32 or 64 bits) and to allow
symbolic offsets such as ‘my_data + 4’ to be used in place of
integer constants. For example, the architectural instruction
lbu
allows only a signed 16-bit offset, whereas the macro
lbu
allows code such as ‘lbu $4,array+32769($5)’.
The implementation of these symbolic offsets depends on several factors,
such as whether the assembler is generating SVR4-style PIC (selected by
-KPIC, see Assembler options), the size of symbols
(see Directives to override the size of symbols),
and the small data limit (see Controlling the use of small data accesses).
Sometimes it is undesirable to have one assembly instruction expand
to several machine instructions. The directive .set nomacro
tells the assembler to warn when this happens. .set macro
restores the default behavior.
Some macro instructions need a temporary register to store intermediate
results. This register is usually $1
, also known as $at
,
but it can be changed to any core register reg using
.set at=
reg. Note that $at
always refers
to $1
regardless of which register is being used as the
temporary register.
Implicit uses of the temporary register in macros could interfere with
explicit uses in the assembly code. The assembler therefore warns
whenever it sees an explicit use of the temporary register. The directive
.set noat
silences this warning while .set at
restores
the default behavior. It is safe to use .set noat
while
.set nomacro
is in effect since single-instruction macros
never need a temporary register.
Note that while the gnu assembler provides these macros for compatibility, it does not make any attempt to optimize them with the surrounding code.
The n64 ABI allows symbols to have any 64-bit value. Although this provides a great deal of flexibility, it means that some macros have much longer expansions than their 32-bit counterparts. For example, the non-PIC expansion of ‘dla $4,sym’ is usually:
lui $4,%highest(sym) lui $1,%hi(sym) daddiu $4,$4,%higher(sym) daddiu $1,$1,%lo(sym) dsll32 $4,$4,0 daddu $4,$4,$1
whereas the 32-bit expansion is simply:
lui $4,%hi(sym) daddiu $4,$4,%lo(sym)
n64 code is sometimes constructed in such a way that all symbolic constants are known to have 32-bit values, and in such cases, it's preferable to use the 32-bit expansion instead of the 64-bit expansion.
You can use the .set sym32
directive to tell the assembler
that, from this point on, all expressions of the form
‘symbol’ or ‘symbol + offset’
have 32-bit values. For example:
.set sym32 dla $4,sym lw $4,sym+16 sw $4,sym+0x8000($4)
will cause the assembler to treat ‘sym’, sym+16
and
sym+0x8000
as 32-bit values. The handling of non-symbolic
addresses is not affected.
The directive .set nosym32
ends a .set sym32
block and
reverts to the normal behavior. It is also possible to change the
symbol size using the command-line options -msym32 and
-mno-sym32.
These options and directives are always accepted, but at present, they have no effect for anything other than n64.
It often takes several instructions to load the address of a symbol. For example, when ‘addr’ is a 32-bit symbol, the non-PIC expansion of ‘dla $4,addr’ is usually:
lui $4,%hi(addr) daddiu $4,$4,%lo(addr)
The sequence is much longer when ‘addr’ is a 64-bit symbol. See Directives to override the size of symbols.
In order to cut down on this overhead, most embedded MIPS systems set aside a 64-kilobyte “small data” area and guarantee that all data of size n and smaller will be placed in that area. The limit n is passed to both the assembler and the linker using the command-line option -G n, see Assembler options. Note that the same value of n must be used when linking and when assembling all input files to the link; any inconsistency could cause a relocation overflow error.
The size of an object in the .bss
section is set by the
.comm
or .lcomm
directive that defines it. The size of
an external object may be set with the .extern
directive. For
example, ‘.extern sym,4’ declares that the object at sym
is 4 bytes in length, while leaving sym
otherwise undefined.
When no -G option is given, the default limit is 8 bytes. The option -G 0 prevents any data from being automatically classified as small.
It is also possible to mark specific objects as small by putting them
in the special sections .sdata
and .sbss
, which are
“small” counterparts of .data
and .bss
respectively.
The toolchain will treat such data as small regardless of the
-G setting.
On startup, systems that support a small data area are expected to
initialize register $28
, also known as $gp
, in such a
way that small data can be accessed using a 16-bit offset from that
register. For example, when ‘addr’ is small data,
the ‘dla $4,addr’ instruction above is equivalent to:
daddiu $4,$28,%gp_rel(addr)
Small data is not supported for SVR4-style PIC.
gnu as
supports an additional directive to change
the MIPS Instruction Set Architecture level on the fly: .set
mips
n. n should be a number from 0 to 5, or 32, 32r2, 32r3,
32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6.
The values other than 0 make the assembler accept instructions
for the corresponding ISA level, from that point on in the
assembly. .set mips
n affects not only which instructions
are permitted, but also how certain macros are expanded. .set
mips0
restores the ISA level to its original level: either the
level you selected with command-line options, or the default for your
configuration. You can use this feature to permit specific MIPS III
instructions while assembling in 32 bit mode. Use this directive with
care!
The .set arch=
cpu directive provides even finer control.
It changes the effective CPU target and allows the assembler to use
instructions specific to a particular CPU. All CPUs supported by the
‘-march’ command-line option are also selectable by this directive.
The original value is restored by .set arch=default
.
The directive .set mips16
puts the assembler into MIPS 16 mode,
in which it will assemble instructions for the MIPS 16 processor. Use
.set nomips16
to return to normal 32 bit mode.
Traditional MIPS assemblers do not support this directive.
The directive .set micromips
puts the assembler into microMIPS mode,
in which it will assemble instructions for the microMIPS processor. Use
.set nomicromips
to return to normal 32 bit mode.
Traditional MIPS assemblers do not support this directive.
The .module
directive allows command-line options to be set directly
from assembly. The format of the directive matches the .set
directive but only those options which are relevant to a whole module are
supported. The effect of a .module
directive is the same as the
corresponding command-line option. Where .set
directives support
returning to a default then the .module
directives do not as they
define the defaults.
These module-level directives must appear first in assembly.
Traditional MIPS assemblers do not support this directive.
The directive .set insn32
makes the assembler only use 32-bit
instruction encodings when generating code for the microMIPS processor.
This directive inhibits the use of any 16-bit instructions from that
point on in the assembly. The .set noinsn32
directive allows
16-bit instructions to be accepted.
Traditional MIPS assemblers do not support this directive.
By default, MIPS 16 instructions are automatically extended to 32 bits
when necessary. The directive .set noautoextend
will turn this
off. When .set noautoextend
is in effect, any 32 bit instruction
must be explicitly extended with the .e
modifier (e.g.,
li.e $4,1000
). The directive .set autoextend
may be used
to once again automatically extend instructions when necessary.
This directive is only meaningful when in MIPS 16 mode. Traditional MIPS assemblers do not support this directive.
The .insn
directive tells as
that the following
data is actually instructions. This makes a difference in MIPS 16 and
microMIPS modes: when loading the address of a label which precedes
instructions, as
automatically adds 1 to the value, so
that jumping to the loaded address will do the right thing.
The .global
and .globl
directives supported by
as
will by default mark the symbol as pointing to a
region of data not code. This means that, for example, any
instructions following such a symbol will not be disassembled by
objdump
as it will regard them as data. To change this
behavior an optional section name can be placed after the symbol name
in the .global
directive. If this section exists and is known
to be a code section, then the symbol will be marked as pointing at
code not data. Ie the syntax for the directive is:
.global
symbol[
section][,
symbol[
section]] ...
,
Here is a short example:
.global foo .text, bar, baz .data foo: nop bar: .word 0x0 baz: .word 0x1
The MIPS ABIs support a variety of different floating-point extensions where calling-convention and register sizes vary for floating-point data. The extensions exist to support a wide variety of optional architecture features. The resulting ABI variants are generally incompatible with each other and must be tracked carefully.
Traditionally the use of an explicit .gnu_attribute 4,
n
directive is used to indicate which ABI is in use by a specific module.
It was then left to the user to ensure that command-line options and the
selected ABI were compatible with some potential for inconsistencies.
The supported floating-point ABI variants are:
0 - No floating-point
1 - Double-precision
2 - Single-precision
3 - Soft-float
4 - Deprecated
5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
6 - Double-precision 32-bit FPU, 64-bit FPU
7 - Double-precision compat 32-bit FPU, 64-bit FPU
In order to simplify and add safety to the process of selecting the
correct floating-point ABI, the assembler will automatically infer the
correct .gnu_attribute 4,
n directive based on command-line
options and .module
overrides. Where an explicit
.gnu_attribute 4,
n directive has been seen then a warning
will be raised if it does not match an inferred setting.
The floating-point ABI is inferred as follows. If ‘-msoft-float’ has been used the module will be marked as soft-float. If ‘-msingle-float’ has been used then the module will be marked as single-precision. The remaining ABIs are then selected based on the FP register width. Double-precision is selected if the width of GP and FP registers match and the special double-precision variants for 32-bit ABIs are then selected depending on ‘-mfpxx’, ‘-mfp64’ and ‘-mno-odd-spreg’.
Modules using the default FP ABI (no floating-point) can be linked with any other (singular) FP ABI variant.
Special compatibility support exists for O32 with the four double-precision FP ABI variants. The ‘-mfpxx’ FP ABI is specifically designed to be compatible with the standard double-precision ABI and the ‘-mfp64’ FP ABIs. This makes it desirable for O32 modules to be built as ‘-mfpxx’ to ensure the maximum compatibility with other modules produced for more specific needs. The only FP ABIs which cannot be linked together are the standard double-precision ABI and the full ‘-mfp64’ ABI with ‘-modd-spreg’.
The IEEE 754 floating-point standard defines two types of not-a-number (NaN) data: “signalling” NaNs and “quiet” NaNs. The original version of the standard did not specify how these two types should be distinguished. Most implementations followed the i387 model, in which the first bit of the significand is set for quiet NaNs and clear for signalling NaNs. However, the original MIPS implementation assigned the opposite meaning to the bit, so that it was set for signalling NaNs and clear for quiet NaNs.
The 2008 revision of the standard formally suggested the i387 choice
and as from Sep 2012 the current release of the MIPS architecture
therefore optionally supports that form. Code that uses one NaN encoding
would usually be incompatible with code that uses the other NaN encoding,
so MIPS ELF objects have a flag (EF_MIPS_NAN2008
) to record which
encoding is being used.
Assembly files can use the .nan
directive to select between the
two encodings. ‘.nan 2008’ says that the assembly file uses the
IEEE 754-2008 encoding while ‘.nan legacy’ says that the file uses
the original MIPS encoding. If several .nan
directives are given,
the final setting is the one that is used.
The command-line options -mnan=legacy and -mnan=2008
can be used instead of ‘.nan legacy’ and ‘.nan 2008’
respectively. However, any .nan
directive overrides the
command-line setting.
‘.nan legacy’ is the default if no .nan
directive or
-mnan option is given.
Note that gnu as
does not produce NaNs itself and
therefore these directives do not affect code generation. They simply
control the setting of the EF_MIPS_NAN2008
flag.
Traditional MIPS assemblers do not support these directives.
The directives .set push
and .set pop
may be used to save
and restore the current settings for all the options which are
controlled by .set
. The .set push
directive saves the
current settings on a stack. The .set pop
directive pops the
stack and restores the settings.
These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.
Traditional MIPS assemblers do not support these directives.
The directive .set mips3d
makes the assembler accept instructions
from the MIPS-3D Application Specific Extension from that point on
in the assembly. The .set nomips3d
directive prevents MIPS-3D
instructions from being accepted.
The directive .set smartmips
makes the assembler accept
instructions from the SmartMIPS Application Specific Extension to the
MIPS32 ISA from that point on in the assembly. The
.set nosmartmips
directive prevents SmartMIPS instructions from
being accepted.
The directive .set mdmx
makes the assembler accept instructions
from the MDMX Application Specific Extension from that point on
in the assembly. The .set nomdmx
directive prevents MDMX
instructions from being accepted.
The directive .set dsp
makes the assembler accept instructions
from the DSP Release 1 Application Specific Extension from that point
on in the assembly. The .set nodsp
directive prevents DSP
Release 1 instructions from being accepted.
The directive .set dspr2
makes the assembler accept instructions
from the DSP Release 2 Application Specific Extension from that point
on in the assembly. This directive implies .set dsp
. The
.set nodspr2
directive prevents DSP Release 2 instructions from
being accepted.
The directive .set dspr3
makes the assembler accept instructions
from the DSP Release 3 Application Specific Extension from that point
on in the assembly. This directive implies .set dsp
and
.set dspr2
. The .set nodspr3
directive prevents DSP
Release 3 instructions from being accepted.
The directive .set mt
makes the assembler accept instructions
from the MT Application Specific Extension from that point on
in the assembly. The .set nomt
directive prevents MT
instructions from being accepted.
The directive .set mcu
makes the assembler accept instructions
from the MCU Application Specific Extension from that point on
in the assembly. The .set nomcu
directive prevents MCU
instructions from being accepted.
The directive .set msa
makes the assembler accept instructions
from the MIPS SIMD Architecture Extension from that point on
in the assembly. The .set nomsa
directive prevents MSA
instructions from being accepted.
The directive .set virt
makes the assembler accept instructions
from the Virtualization Application Specific Extension from that point
on in the assembly. The .set novirt
directive prevents Virtualization
instructions from being accepted.
The directive .set xpa
makes the assembler accept instructions
from the XPA Extension from that point on in the assembly. The
.set noxpa
directive prevents XPA instructions from being accepted.
The directive .set mips16e2
makes the assembler accept instructions
from the MIPS16e2 Application Specific Extension from that point on in the
assembly, whenever in MIPS16 mode. The .set nomips16e2
directive
prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. Neither
directive affects the state of MIPS16 mode being active itself which has
separate controls.
The directive .set crc
makes the assembler accept instructions
from the CRC Extension from that point on in the assembly. The
.set nocrc
directive prevents CRC instructions from being accepted.
The directive .set ginv
makes the assembler accept instructions
from the GINV Extension from that point on in the assembly. The
.set noginv
directive prevents GINV instructions from being accepted.
The directive .set loongson-mmi
makes the assembler accept
instructions from the MMI Extension from that point on in the assembly.
The .set noloongson-mmi
directive prevents MMI instructions from
being accepted.
The directive .set loongson-cam
makes the assembler accept
instructions from the Loongson CAM from that point on in the assembly.
The .set noloongson-cam
directive prevents Loongson CAM instructions
from being accepted.
The directive .set loongson-ext
makes the assembler accept
instructions from the Loongson EXT from that point on in the assembly.
The .set noloongson-ext
directive prevents Loongson EXT instructions
from being accepted.
The directive .set loongson-ext2
makes the assembler accept
instructions from the Loongson EXT2 from that point on in the assembly.
This directive implies .set loognson-ext
.
The .set noloongson-ext2
directive prevents Loongson EXT2 instructions
from being accepted.
Traditional MIPS assemblers do not support these directives.
The directives .set softfloat
and .set hardfloat
provide
finer control of disabling and enabling float-point instructions.
These directives always override the default (that hard-float
instructions are accepted) or the command-line options
(‘-msoft-float’ and ‘-mhard-float’).
The directives .set singlefloat
and .set doublefloat
provide finer control of disabling and enabling double-precision
float-point operations. These directives always override the default
(that double-precision operations are accepted) or the command-line
options (‘-msingle-float’ and ‘-mdouble-float’).
Traditional MIPS assemblers do not support these directives.
The presence of a ‘#’ on a line indicates the start of a comment that extends to the end of the current line.
If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘;’ character can be used to separate statements on the same line.
The MMIX version of as
has some machine-dependent options.
When ‘--fixed-special-register-names’ is specified, only the register
names specified in MMIX-Regs are recognized in the instructions
PUT
and GET
.
You can use the ‘--globalize-symbols’ to make all symbols global.
This option is useful when splitting up a mmixal
program into
several files.
The ‘--gnu-syntax’ turns off most syntax compatibility with
mmixal
. Its usability is currently doubtful.
The ‘--relax’ option is not fully supported, but will eventually make the object file prepared for linker relaxation.
If you want to avoid inadvertently calling a predefined symbol and would
rather get an error, for example when using as
with a
compiler or other machine-generated code, specify
‘--no-predefined-syms’. This turns off built-in predefined
definitions of all such symbols, including rounding-mode symbols, segment
symbols, ‘BIT’ symbols, and TRAP
symbols used in mmix
“system calls”. It also turns off predefined special-register names,
except when used in PUT
and GET
instructions.
By default, some instructions are expanded to fit the size of the operand or an external symbol (see MMIX-Expand). By passing ‘--no-expand’, no such expansion will be done, instead causing errors at link time if the operand does not fit.
The mmixal
documentation (see mmixsite) specifies that global
registers allocated with the ‘GREG’ directive (see MMIX-greg) and
initialized to the same non-zero value, will refer to the same global
register. This isn't strictly enforceable in as
since the
final addresses aren't known until link-time, but it will do an effort
unless the ‘--no-merge-gregs’ option is specified. (Register merging
isn't yet implemented in ld
.)
as
will warn every time it expands an instruction to fit an
operand unless the option ‘-x’ is specified. It is believed that
this behaviour is more useful than just mimicking mmixal
's
behaviour, in which instructions are only expanded if the ‘-x’ option
is specified, and assembly fails otherwise, when an instruction needs to
be expanded. It needs to be kept in mind that mmixal
is both an
assembler and linker, while as
will expand instructions
that at link stage can be contracted. (Though linker relaxation isn't yet
implemented in ld
.) The option ‘-x’ also implies
‘--linker-allocated-gregs’.
If instruction expansion is enabled, as
can expand a
‘PUSHJ’ instruction into a series of instructions. The shortest
expansion is to not expand it, but just mark the call as redirectable to a
stub, which ld
creates at link-time, but only if the
original ‘PUSHJ’ instruction is found not to reach the target. The
stub consists of the necessary instructions to form a jump to the target.
This happens if as
can assert that the ‘PUSHJ’
instruction can reach such a stub. The option ‘--no-pushj-stubs’
disables this shorter expansion, and the longer series of instructions is
then created at assembly-time. The option ‘--no-stubs’ is a synonym,
intended for compatibility with future releases, where generation of stubs
for other instructions may be implemented.
Usually a two-operand-expression (see GREG-base) without a matching
‘GREG’ directive is treated as an error by as
. When
the option ‘--linker-allocated-gregs’ is in effect, they are instead
passed through to the linker, which will allocate as many global registers
as is needed.
When as
encounters an instruction with an operand that is
either not known or does not fit the operand size of the instruction,
as
(and ld
) will expand the instruction into
a sequence of instructions semantically equivalent to the operand fitting
the instruction. Expansion will take place for the following
instructions:
SETL
, INCML
,
INCMH
and INCH
. The operand must be a multiple of four.
$255
to the operand value, which like with GETA
must
be a multiple of four, and a final GO $255,$255,0
.
$255
to the operand value, followed by a PUSHGO $255,$255,0
.
PUSHJ
. The final instruction
is GO $255,$255,0
.
The linker ld
is expected to shrink these expansions for
code assembled with ‘--relax’ (though not currently implemented).
The assembly syntax is supposed to be upward compatible with that described in Sections 1.3 and 1.4 of ‘The Art of Computer Programming, Volume 1’. Draft versions of those chapters as well as other MMIX information is located at http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html. Most code examples from the mmixal package located there should work unmodified when assembled and linked as single files, with a few noteworthy exceptions (see MMIX-mmixal).
Before an instruction is emitted, the current location is aligned to the next four-byte boundary. If a label is defined at the beginning of the line, its value will be the aligned value.
In addition to the traditional hex-prefix ‘0x’, a hexadecimal number can also be specified by the prefix character ‘#’.
After all operands to an MMIX instruction or directive have been specified, the rest of the line is ignored, treated as a comment.
The characters ‘*’ and ‘#’ are line comment characters; each start a comment at the beginning of a line, but only at the beginning of a line. A ‘#’ prefixes a hexadecimal number if found elsewhere on a line. If a ‘#’ appears at the start of a line the whole line is treated as a comment, but the line can also act as a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
Two other characters, ‘%’ and ‘!’, each start a comment anywhere on the line. Thus you can't use the ‘modulus’ and ‘not’ operators in expressions normally associated with these two characters.
A ‘;’ is a line separator, treated as a new-line, so separate instructions can be specified on a single line.
The character ‘:’ is permitted in identifiers. There are two exceptions to it being treated as any other symbol character: if a symbol begins with ‘:’, it means that the symbol is in the global namespace and that the current prefix should not be prepended to that symbol (see MMIX-prefix). The ‘:’ is then not considered part of the symbol. For a symbol in the label position (first on a line), a ‘:’ at the end of a symbol is silently stripped off. A label is permitted, but not required, to be followed by a ‘:’, as with many other assembly formats.
The character ‘@’ in an expression, is a synonym for ‘.’, the current location.
In addition to the common forward and backward local symbol formats (see Symbol Names), they can be specified with upper-case ‘B’ and ‘F’, as in ‘8B’ and ‘9F’. A local label defined for the current position is written with a ‘H’ appended to the number:
3H LDB $0,$1,2
This and traditional local-label formats cannot be mixed: a label must be defined and referred to using the same format.
There's a minor caveat: just as for the ordinary local symbols, the local symbols are translated into ordinary symbols using control characters are to hide the ordinal number of the symbol. Unfortunately, these symbols are not translated back in error messages. Thus you may see confusing error messages when local symbols are used. Control characters ‘\003’ (control-C) and ‘\004’ (control-D) are used for the MMIX-specific local-symbol syntax.
The symbol ‘Main’ is handled specially; it is always global.
By defining the symbols ‘__.MMIX.start..text’ and ‘__.MMIX.start..data’, the address of respectively the ‘.text’ and ‘.data’ segments of the final program can be defined, though when linking more than one object file, the code or data in the object file containing the symbol is not guaranteed to be start at that position; just the final executable. See MMIX-loc.
Local and global registers are specified as ‘$0’ to ‘$255’. The recognized special register names are ‘rJ’, ‘rA’, ‘rB’, ‘rC’, ‘rD’, ‘rE’, ‘rF’, ‘rG’, ‘rH’, ‘rI’, ‘rK’, ‘rL’, ‘rM’, ‘rN’, ‘rO’, ‘rP’, ‘rQ’, ‘rR’, ‘rS’, ‘rT’, ‘rU’, ‘rV’, ‘rW’, ‘rX’, ‘rY’, ‘rZ’, ‘rBB’, ‘rTT’, ‘rWW’, ‘rXX’, ‘rYY’ and ‘rZZ’. A leading ‘:’ is optional for special register names.
Local and global symbols can be equated to register names and used in place of ordinary registers.
Similarly for special registers, local and global symbols can be used.
Also, symbols equated from numbers and constant expressions are allowed in
place of a special register, except when either of the options
--no-predefined-syms
and --fixed-special-register-names
are
specified. Then only the special register names above are allowed for the
instructions having a special register operand; GET
and PUT
.
LOC
LOC
directive sets the current location to the value of the
operand field, which may include changing sections. If the operand is a
constant, the section is set to either .data
if the value is
0x2000000000000000
or larger, else it is set to .text
.
Within a section, the current location may only be changed to
monotonically higher addresses. A LOC expression must be a previously
defined symbol or a “pure” constant.
An example, which sets the label prev to the current location, and updates the current location to eight bytes forward:
prev LOC @+8
When a LOC has a constant as its operand, a symbol
__.MMIX.start..text
or __.MMIX.start..data
is defined
depending on the address as mentioned above. Each such symbol is
interpreted as special by the linker, locating the section at that
address. Note that if multiple files are linked, the first object file
with that section will be mapped to that address (not necessarily the file
with the LOC definition).
LOCAL
LOCAL external_symbol LOCAL 42 .local asymbol
This directive-operation generates a link-time assertion that the operand
does not correspond to a global register. The operand is an expression
that at link-time resolves to a register symbol or a number. A number is
treated as the register having that number. There is one restriction on
the use of this directive: the pseudo-directive must be placed in a
section with contents, code or data.
IS
IS
directive:
asymbol IS an_expression
sets the symbol ‘asymbol’ to ‘an_expression’. A symbol may not be set more than once using this directive. Local labels may be set using this directive, for example:
5H IS @+4
GREG
areg GREG breg GREG data_value GREG data_buffer .greg creg, another_data_value
The symbolic register name can be used in place of a (non-special)
register. If a value isn't provided, it defaults to zero. Unless the
option ‘--no-merge-gregs’ is specified, non-zero registers allocated
with this directive may be eliminated by as
; another
register with the same value used in its place.
Any of the instructions
‘CSWAP’,
‘GO’,
‘LDA’,
‘LDBU’,
‘LDB’,
‘LDHT’,
‘LDOU’,
‘LDO’,
‘LDSF’,
‘LDTU’,
‘LDT’,
‘LDUNC’,
‘LDVTS’,
‘LDWU’,
‘LDW’,
‘PREGO’,
‘PRELD’,
‘PREST’,
‘PUSHGO’,
‘STBU’,
‘STB’,
‘STCO’,
‘STHT’,
‘STOU’,
‘STSF’,
‘STTU’,
‘STT’,
‘STUNC’,
‘SYNCD’,
‘SYNCID’,
can have a value nearby an initial value in place of its
second and third operands. Here, “nearby” is defined as within the
range 0...255 from the initial value of such an allocated register.
buffer1 BYTE 0,0,0,0,0 buffer2 BYTE 0,0,0,0,0 ... GREG buffer1 LDOU $42,buffer2
In the example above, the ‘Y’ field of the LDOUI
instruction
(LDOU with a constant Z) will be replaced with the global register
allocated for ‘buffer1’, and the ‘Z’ field will have the value
5, the offset from ‘buffer1’ to ‘buffer2’. The result is
equivalent to this code:
buffer1 BYTE 0,0,0,0,0 buffer2 BYTE 0,0,0,0,0 ... tmpreg GREG buffer1 LDOU $42,tmpreg,(buffer2-buffer1)
Global registers allocated with this directive are allocated in order
higher-to-lower within a file. Other than that, the exact order of
register allocation and elimination is undefined. For example, the order
is undefined when more than one file with such directives are linked
together. With the options ‘-x’ and ‘--linker-allocated-gregs’,
‘GREG’ directives for two-operand cases like the one mentioned above
can be omitted. Sufficient global registers will then be allocated by the
linker.
BYTE
WYDE
TETRA
OCTA
PREFIX
PREFIX a PREFIX b c IS 0
defines a symbol ‘abc’ with the value 0.
BSPEC
ESPEC
BSPEC 42 TETRA 1,2,3 ESPEC
The single operand to ‘BSPEC’ must be number in the range 0...255. The ‘BSPEC’ number 80 is used by the GNU binutils implementation.
mmixal
The binutils as
and ld
combination has a few
differences in function compared to mmixal
(see mmixsite).
The replacement of a symbol with a GREG-allocated register
(see GREG-base) is not handled the exactly same way in
as
as in mmixal
. This is apparent in the
mmixal
example file inout.mms
, where different registers
with different offsets, eventually yielding the same address, are used in
the first instruction. This type of difference should however not affect
the function of any program unless it has specific assumptions about the
allocated register number.
Line numbers (in the ‘mmo’ object format) are currently not supported.
Expression operator precedence is not that of mmixal: operator precedence is that of the C programming language. It's recommended to use parentheses to explicitly specify wanted operator precedence whenever more than one type of operators are used.
The serialize unary operator &
, the fractional division operator
‘//’, the logical not operator !
and the modulus operator
‘%’ are not available.
Symbols are not global by default, unless the option ‘--globalize-symbols’ is passed. Use the ‘.global’ directive to globalize symbols (see Global).
Operand syntax is a bit stricter with as
than
mmixal
. For example, you can't say addu 1,2,3
, instead you
must write addu $1,$2,3
.
You can't LOC to a lower address than those already visited (i.e., “backwards”).
A LOC directive must come before any emitted code.
Predefined symbols are visible as file-local symbols after use. (In the ELF file, that is—the linked mmo file has no notion of a file-local symbol.)
Some mapping of constant expressions to sections in LOC expressions is
attempted, but that functionality is easily confused and should be avoided
unless compatibility with mmixal
is required. A LOC expression to
‘0x2000000000000000’ or higher, maps to the ‘.data’ section and
lower addresses map to the ‘.text’ section (see MMIX-loc).
The code and data areas are each contiguous. Sparse programs with
far-away LOC directives will take up the same amount of space as a
contiguous program with zeros filled in the gaps between the LOC
directives. If you need sparse programs, you might try and get the wanted
effect with a linker script and splitting up the code parts into sections
(see Section). Assembly code for this, to be compatible with
mmixal
, would look something like:
.if 0 LOC away_expression .else .section away,"ax" .fi
as
will not execute the LOC directive and mmixal
ignores the lines with .
. This construct can be used generally to
help compatibility.
Symbols can't be defined twice–not even to the same value.
Instruction mnemonics are recognized case-insensitive, though the ‘IS’ and ‘GREG’ pseudo-operations must be specified in upper-case characters.
There's no unicode support.
The following is a list of programs in ‘mmix.tar.gz’, available at
http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html, last
checked with the version dated 2001-08-25 (md5sum
c393470cfc86fac040487d22d2bf0172) that assemble with mmixal
but do
not assemble with as
:
silly.mms
sim.mms
test.mms
-mmcu
-mcpu
-msilicon-errata=
name[,
name...]
cpu4
PUSH #4
and PUSH #8 need longer encodings on the
MSP430. This option is enabled by default, and cannot be disabled.
cpu8
SP
to an odd value.
cpu11
SR
and the PC
in the same instruction.
cpu12
PC
in a CMP
or BIT
instruction.
cpu13
SR
.
cpu19
NOP
after CPUOFF
.
-msilicon-errata-warn=
name[,
name...]
-mP
-mQ
-ml
-mn
EINT
, DINT
, BIC #8,
SR
, BIS #8, SR
or MOV.W <>, SR
) must be
followed by a NOP instruction in order to ensure the correct
processing of interrupts. By default it is up to the programmer to
supply these NOP instructions, but this command-line option enables
the automatic insertion by the assembler, if they are missing.
-mN
-my
Note that this option can be stacked with the -mn option so
that the assembler will both warn about missing NOP instructions and
then insert them automatically.
-mY
-md
-mdata-region=
regionnone
lower
upper
either
The macro syntax used on the MSP 430 is like that described in the MSP
430 Family Assembler Specification. Normal as
macros should still work.
Additional built-in macros are:
llo(exp)
lhi(exp)
hlo(exp)
hhi(exp)
They normally being used as an immediate source operand.
mov #llo(1), r10 ; == mov #1, r10 mov #lhi(1), r10 ; == mov #0, r10
A semicolon (‘;’) appearing anywhere on a line starts a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but it can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
Multiple statements can appear on the same line provided that they are separated by the ‘{’ character.
The character ‘$’ in jump instructions indicates current location and implemented only for TI syntax compatibility.
General-purpose registers are represented by predefined symbols of the
form ‘rN’ (for global registers), where N represents
a number between 0
and 15
. The leading
letters may be in either upper or lower case; for example, ‘r13’
and ‘R7’ are both valid register names.
Register names ‘PC’, ‘SP’ and ‘SR’ cannot be used as register names and will be treated as variables. Use ‘r0’, ‘r1’, and ‘r2’ instead.
@rN
0(rN)
jCOND +N
Also, there are some instructions, which cannot be found in other assemblers. These are branch instructions, which has different opcodes upon jump distance. They all got PC relative addressing mode.
beq label
jne $+6 br label
bne label
blt label
bltn label
bltu label
bge label
bgeu label
bgt label
bgtu label
bleu label
ble label
jump label
The MSP 430 family uses ieee 32-bit floating-point numbers.
.file
Warning: in other versions of the gnu assembler,.file
is used for the directive called.app-file
in the MSP 430 support.
.line
.arch
.cpu
.profiler
.refsym
.mspabi_attribute
OFBA_MSPABI_Tag_ISA
to MSP430X
:
‘.mspabi_attribute 4, 2’
See the MSP430 EABI, document slaa534 for the details on tag names and values.
as
implements all the standard MSP 430 opcodes. No
additional pseudo-instructions are needed on this family.
For information on the 430 machine instruction set, see MSP430 User's Manual, document slau049d, Texas Instrument, Inc.
It is a performance hit to use gcc's profiling approach for this tiny target. Even more – jtag hardware facility does not perform any profiling functions. However we've got gdb's built-in simulator where we can do anything.
We define new section ‘.profiler’ which holds all profiling information. We define new pseudo operation ‘.profiler’ which will instruct assembler to add new profile entry to the object file. Profile should take place at the present address.
Pseudo operation format:
‘.profiler flags,function_to_profile [, cycle_corrector, extra]’
where:
s
x
i
f
l
c
d
I
P
p
E
e
j
a
t
function_to_profile
cycle_corrector
extra
For example:
.global fxx .type fxx,@function fxx: .LFrameOffset_fxx=0x08 .profiler "scdP", fxx ; function entry. ; we also demand stack value to be saved push r11 push r10 push r9 push r8 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point ; (this is a prologue end) ; note, that spare var filled with ; the farme size mov r15,r8 ... .profiler cdE,fxx ; check stack pop r8 pop r9 pop r10 pop r11 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter ret ; cause 'ret' insn takes 3 cycles
The presence of a ‘#’ appearing anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
If Sequent compatibility has been configured into the assembler then the ‘|’ character appearing as the first character on a line will also indicate the start of a line comment.
The ‘;’ character can be used to separate statements on the same line.
The PDP-11 version of as
has a rich set of machine
dependent options.
-mpic | -mno-pic
The default is to generate position-independent code.
These options enables or disables the use of extensions over the base
line instruction set as introduced by the first PDP-11 CPU: the KA11.
Most options come in two variants: a -m
extension that
enables extension, and a -mno-
extension that disables
extension.
The default is to enable all extensions.
-mall | -mall-extensions
-mno-extensions
-mcis | -mno-cis
ADDNI
, ADDN
, ADDPI
,
ADDP
, ASHNI
, ASHN
, ASHPI
, ASHP
,
CMPCI
, CMPC
, CMPNI
, CMPN
, CMPPI
,
CMPP
, CVTLNI
, CVTLN
, CVTLPI
, CVTLP
,
CVTNLI
, CVTNL
, CVTNPI
, CVTNP
, CVTPLI
,
CVTPL
, CVTPNI
, CVTPN
, DIVPI
, DIVP
,
L2DR
, L3DR
, LOCCI
, LOCC
, MATCI
,
MATC
, MOVCI
, MOVC
, MOVRCI
, MOVRC
,
MOVTCI
, MOVTC
, MULPI
, MULP
, SCANCI
,
SCANC
, SKPCI
, SKPC
, SPANCI
, SPANC
,
SUBNI
, SUBN
, SUBPI
, and SUBP
.
-mcsm | -mno-csm
CSM
instruction.
-meis | -mno-eis
ASHC
, ASH
, DIV
,
MARK
, MUL
, RTT
, SOB
SXT
, and
XOR
.
-mfis | -mkev11
-mno-fis | -mno-kev11
FADD
, FDIV
, FMUL
, and FSUB
.
-mfpp | -mfpu | -mfp-11
-mno-fpp | -mno-fpu | -mno-fp-11
ABSF
, ADDF
, CFCC
, CLRF
, CMPF
,
DIVF
, LDCFF
, LDCIF
, LDEXP
, LDF
,
LDFPS
, MODF
, MULF
, NEGF
, SETD
,
SETF
, SETI
, SETL
, STCFF
, STCFI
,
STEXP
, STF
, STFPS
, STST
, SUBF
, and
TSTF
.
-mlimited-eis | -mno-limited-eis
MARK
, RTT
, SOB
, SXT
, and XOR
.
The -mno-limited-eis options also implies -mno-eis.
-mmfpt | -mno-mfpt
MFPT
instruction.
-mmultiproc | -mno-multiproc
TSTSET
and
WRTLCK
.
-mmxps | -mno-mxps
MFPS
and MTPS
instructions.
-mspl | -mno-spl
SPL
instruction.
Enable (or disable) the use of the microcode instructions: LDUB
,
MED
, and XFC
.
These options enable the instruction set extensions supported by a particular CPU, and disables all other extensions.
-mka11
-mkb11
SPL
.
-mkd11a
-mkd11b
-mkd11d
-mkd11e
MFPS
, and MTPS
.
-mkd11f | -mkd11h | -mkd11q
MFPS
, and MTPS
.
-mkd11k
LDUB
, MED
,
MFPS
, MFPT
, MTPS
, and XFC
.
-mkd11z
CSM
, MFPS
,
MFPT
, MTPS
, and SPL
.
-mf11
MFPS
, MFPT
, and
MTPS
.
-mj11
CSM
, MFPS
,
MFPT
, MTPS
, SPL
, TSTSET
, and WRTLCK
.
-mt11
MFPS
, and
MTPS
.
These options enable the instruction set extensions supported by a particular machine model, and disables all other extensions.
-m11/03
-mkd11f
.
-m11/04
-mkd11d
.
-m11/05 | -m11/10
-mkd11b
.
-m11/15 | -m11/20
-mka11
.
-m11/21
-mt11
.
-m11/23 | -m11/24
-mf11
.
-m11/34
-mkd11e
.
-m11/34a
-mkd11e
-mfpp
.
-m11/35 | -m11/40
-mkd11a
.
-m11/44
-mkd11z
.
-m11/45 | -m11/50 | -m11/55 | -m11/70
-mkb11
.
-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94
-mj11
.
-m11/60
-mkd11k
.
The PDP-11 version of as
has a few machine
dependent assembler directives.
.bss
bss
section.
.even
as
supports both DEC syntax and BSD syntax. The only
difference is that in DEC syntax, a #
character is used to denote
an immediate constants, while in BSD syntax the character for this
purpose is $
.
general-purpose registers are named r0
through r7
.
Mnemonic alternatives for r6
and r7
are sp
and
pc
, respectively.
Floating-point registers are named ac0
through ac3
, or
alternatively fr0
through fr3
.
Comments are started with a #
or a /
character, and extend
to the end of the line. (FIXME: clash with immediates?)
Multiple statements on the same line can be separated by the ‘;’ character.
Some instructions have alternative names.
BCC
BHIS
BCS
BLO
L2DR
L2D
L3DR
L3D
SYS
TRAP
The JBR
and J
CC synthetic instructions are not
supported yet.
as
has two additional command-line options for the picoJava
architecture.
-ml
-mb
The presence of a ‘!’ or ‘/’ on a line indicates the start of a comment that extends to the end of the current line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘;’ character can be used to separate statements on the same line.
The PowerPC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.
The following table lists all available PowerPC options.
-a32
-a64
-K PIC
-mpwrx | -mpwr2
-mpwr
-m601
-mppc, -mppc32, -m603, -m604
-m403, -m405
-m440
-m464
-m476
-m7400, -m7410, -m7450, -m7455
-m750cl, -mgekko, -mbroadway
-m821, -m850, -m860
-mppc64, -m620
-me500, -me500x2
-me500mc
-me500mc64
-me5500
-me6500
-mspe
-mspe2
-mtitan
-mppc64bridge
-mbooke
-ma2
-me300
-maltivec
-mvle
-mvsx
-mhtm
-mpower4, -mpwr4
-mpower5, -mpwr5, -mpwr5x
-mpower6, -mpwr6
-mpower7, -mpwr7
-mpower8, -mpwr8
-mpower9, -mpwr9
-mcell
-mcell
-mcom
-many
-mregnames
-mno-regnames
-mrelocatable
-mrelocatable-lib
-memb
-mlittle, -mlittle-endian, -le
-mbig, -mbig-endian, -be
-msolaris
-mno-solaris
-nops=
countA number of assembler directives are available for PowerPC. The following table is far from complete.
.machine "string"
"string"
may be any of the -m cpu selection options
(without the -m) enclosed in double quotes, "push"
, or
"pop"
. .machine "push"
saves the currently selected
cpu, which may be restored with .machine "pop"
.
The presence of a ‘#’ on a line indicates the start of a comment that extends to the end of the current line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
If the assembler has been configured for the ppc-*-solaris* target then the ‘!’ character also acts as a line comment character. This can be disabled via the -mno-solaris command-line option.
The ‘;’ character can be used to separate statements on the same line.
relax
norelax
mg10
mg13
mg14
mrl78
m32bit-doubles
double
floating point type. This is the default.
m64bit-doubles
double
floating point type.
The RL78 has three modifiers that adjust the relocations used by the linker:
%lo16()
movw ax,#%lo16(_sym)
%hi16()
movw ax,#%hi16(_sym)
%hi8()
mov es, #%hi8(_sym)
In addition to the common directives, the RL78 adds these:
.double
.bss
.3byte
.int
.word
The presence of a ‘;’ appearing anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘|’ character can be used to separate statements on the same line.
The Renesas RX port of as
has a few target specific
command-line options:
-m32bit-doubles
-m64bit-doubles
-mbig-endian
-mlittle-endian
-muse-conventional-section-names
-muse-renesas-section-names
-msmall-data-limit
__gp
for
use by the relocations that are needed to support the small data limit
feature. This option is not enabled by default as it would otherwise
pollute the symbol table.
-mpid
__pid_base
,
and also setting the RX_PID flag bit in the e_flags field of the ELF
header of the object file.
-mint-register=
num%gpreg
and %pidreg
meta registers.
-mgcc-abi
-mrx-abi
-mcpu=
namerx100
, rx200
, rx600
, rx610
, rxv2
,
rxv3
and rxv3-dfpu
are recognised as valid cpu names.
Attempting to assemble an instructionnot supported by the indicated
cpu type will result in an error message being generated.
-mno-allow-string-insns
SMOVF
, SCMPU
, SMOVB
, SMOVU
, SUNTIL
SWHILE
or the RMPA
instruction. In addition the mark
tells the linker to complain if an attempt is made to link the binary
with another one that does use any of these instructions.
Note - the inverse of this option, -mallow-string-insns
, is
not needed. The assembler automatically detects the use of the
the instructions in the source code and labels the resulting
object file appropriately. If no string instructions are detected
then the object file is labelled as being one that can be linked with
either string-using or string-banned object files.
The assembler supports one modifier when using symbol addresses in RX instruction operands. The general syntax is the following:
%gp(symbol)
The modifier returns the offset from the __gp symbol to the specified symbol as a 16-bit value. The intent is that this offset should be used in a register+offset move instruction when generating references to small data. Ie, like this:
mov.W %gp(_foo)[%gpreg], r1
The assembler also supports two meta register names which can be used to refer to registers whose values may not be known to the programmer. These meta register names are:
Both registers normally have the value r13, but this can change if some registers have been reserved for use by interrupt handlers or if both the small data limit and position independent data features are being used at the same time.
The RX version of as
has the following specific
assembler directives:
.3byte
.fetchalign
The floating point formats generated by directives are these.
.float
Single
precision (32-bit) floating point constants.
.double
double
directive generates double
precision
(64-bit) floating point constants, otherwise it generates
single
precision (32-bit) floating point constants. To force
the generation of 64-bit floating point constants used the dc.d
directive instead.
The presence of a ‘;’ appearing anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘!’ character can be used to separate statements on the same line.
The s390 version of as
supports two architectures modes
and eleven chip levels. The architecture modes are the Enterprise System
Architecture (ESA) and the newer z/Architecture mode. The chip levels
are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13
(or arch11), z14 (or arch12), and z15 (or arch13).
The following table lists all available s390 specific options:
-m31 | -m64
These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 31-bit platform you must add –enable-64-bit-bfd on the call to the configure script to enable 64-bit usage and use s390x as target platform).
-mesa | -mzarch
The 64-bit instructions are only available with the z/Architecture mode. The combination of ‘-m64’ and ‘-mesa’ results in a warning message.
-march=
CPUg5
(or arch3
),
g6
,
z900
(or arch5
),
z990
(or arch6
),
z9-109
,
z9-ec
(or arch7
),
z10
(or arch8
),
z196
(or arch9
),
zEC12
(or arch10
),
z13
(or arch11
),
z14
(or arch12
), and
z15
(or arch13
).
Assembling an instruction that is not supported on the target processor results in an error message.
The processor names starting with arch
refer to the edition
number in the Principle of Operations manual. They can be used as
alternate processor names and have been added for compatibility with
the IBM XL compiler.
arch3
, g5
and g6
cannot be used with the
‘-mzarch’ option since the z/Architecture mode is not supported
on these processor levels.
There is no arch4
option supported. arch4
matches
-march=arch5 -mesa
.
-mregnames
-mno-regnames
-mwarn-areg-zero
‘#’ is the line comment character.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘;’ character can be used instead of a newline to separate statements.
The assembler syntax closely follows the syntax outlined in Enterprise Systems Architecture/390 Principles of Operation (SA22-7201) and the z/Architecture Principles of Operation (SA22-7832).
Each instruction has two major parts, the instruction mnemonic and the instruction operands. The instruction format varies.
The as
recognizes a number of predefined symbols for the
various processor registers. A register specification in one of the
instruction formats is an unsigned integer between 0 and 15. The specific
instruction and the position of the register in the instruction format
denotes the type of the register. The register symbols are prefixed with
‘%’:
%rN | the 16 general purpose registers, 0 <= N <= 15
|
%fN | the 16 floating point registers, 0 <= N <= 15
|
%aN | the 16 access registers, 0 <= N <= 15
|
%cN | the 16 control registers, 0 <= N <= 15
|
%lit | an alias for the general purpose register %r13
|
%sp | an alias for the general purpose register %r15
|
All instructions documented in the Principles of Operation are supported with the mnemonic and order of operands as described. The instruction mnemonic identifies the instruction format (s390 Formats) and the specific operation code for the instruction. For example, the ‘lr’ mnemonic denotes the instruction format ‘RR’ with the operation code ‘0x18’.
The definition of the various mnemonics follows a scheme, where the first character usually hint at the type of the instruction:
a | add instruction, for example ‘al’ for add logical 32-bit
|
b | branch instruction, for example ‘bc’ for branch on condition
|
c | compare or convert instruction, for example ‘cr’ for compare
register 32-bit
|
d | divide instruction, for example ‘dlr’ devide logical register
64-bit to 32-bit
|
i | insert instruction, for example ‘ic’ insert character
|
l | load instruction, for example ‘ltr’ load and test register
|
mv | move instruction, for example ‘mvc’ move character
|
m | multiply instruction, for example ‘mh’ multiply halfword
|
n | and instruction, for example ‘ni’ and immediate
|
o | or instruction, for example ‘oc’ or character
|
sla, sll | shift left single instruction
|
sra, srl | shift right single instruction
|
st | store instruction, for example ‘stm’ store multiple
|
s | subtract instruction, for example ‘slr’ subtract
logical 32-bit
|
t | test or translate instruction, of example ‘tm’ test under mask
|
x | exclusive or instruction, for example ‘xc’ exclusive or
character
|
Certain characters at the end of the mnemonic may describe a property of the instruction:
c | the instruction uses a 8-bit character operand
|
f | the instruction extends a 32-bit operand to 64 bit
|
g | the operands are treated as 64-bit values
|
h | the operand uses a 16-bit halfword operand
|
i | the instruction uses an immediate operand
|
l | the instruction uses unsigned, logical operands
|
m | the instruction uses a mask or operates on multiple values
|
r | if r is the last character, the instruction operates on registers
|
y | the instruction uses 20-bit displacements
|
There are many exceptions to the scheme outlined in the above lists, in particular for the privileged instructions. For non-privileged instruction it works quite well, for example the instruction ‘clgfr’ c: compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to 64-bit extension, r: register operands. The instruction compares an 64-bit value in a register with the zero extended 32-bit value from a second register. For a complete list of all mnemonics see appendix B in the Principles of Operation.
Instruction operands can be grouped into three classes, operands located in registers, immediate operands, and operands in storage.
A register operand can be located in general, floating-point, access, or control register. The register is identified by a four-bit field. The field containing the register operand is called the R field.
Immediate operands are contained within the instruction and can have 8, 16 or 32 bits. The field containing the immediate operand is called the I field. Dependent on the instruction the I field is either signed or unsigned.
A storage operand consists of an address and a length. The address of a storage operands can be specified in any of these ways:
The length of a storage operand can be:
The notation for storage operand addresses formed from multiple fields is as follows:
Dn(Bn)
Dn(Xn,Bn)
Dn(Ln,Bn)
The base registers Bn and the index registers Xn of a storage operand can be skipped. If Bn and Xn are skipped, a zero will be stored to the operand field. The notation changes as follows:
full notation | short notation
|
---|---|
Dn(0,Bn) | Dn(Bn)
|
Dn(0,0) | Dn
|
Dn(0) | Dn
|
Dn(Ln,0) | Dn(Ln)
|
The Principles of Operation manuals lists 26 instruction formats where some of the formats have multiple variants. For the ‘.insn’ pseudo directive the assembler recognizes some of the formats. Typically, the most general variant of the instruction format is used by the ‘.insn’ directive.
The following table lists the abbreviations used in the table of instruction formats:
OpCode / OpCd | Part of the op code.
|
Bx | Base register number for operand x.
|
Dx | Displacement for operand x.
|
DLx | Displacement lower 12 bits for operand x.
|
DHx | Displacement higher 8-bits for operand x.
|
Rx | Register number for operand x.
|
Xx | Index register number for operand x.
|
Ix | Signed immediate for operand x.
|
Ux | Unsigned immediate for operand x.
|
An instruction is two, four, or six bytes in length and must be aligned on a 2 byte boundary. The first two bits of the instruction specify the length of the instruction, 00 indicates a two byte instruction, 01 and 10 indicates a four byte instruction, and 11 indicates a six byte instruction.
The following table lists the s390 instruction formats that are available with the ‘.insn’ pseudo directive:
E format
+-------------+ | OpCode | +-------------+ 0 15
RI format: <insn> R1,I2
+--------+----+----+------------------+ | OpCode | R1 |OpCd| I2 | +--------+----+----+------------------+ 0 8 12 16 31
RIE format: <insn> R1,R3,I2
+--------+----+----+------------------+--------+--------+ | OpCode | R1 | R3 | I2 |////////| OpCode | +--------+----+----+------------------+--------+--------+ 0 8 12 16 32 40 47
RIL format: <insn> R1,I2
+--------+----+----+------------------------------------+ | OpCode | R1 |OpCd| I2 | +--------+----+----+------------------------------------+ 0 8 12 16 47
RILU format: <insn> R1,U2
+--------+----+----+------------------------------------+ | OpCode | R1 |OpCd| U2 | +--------+----+----+------------------------------------+ 0 8 12 16 47
RIS format: <insn> R1,I2,M3,D4(B4)
+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 36 47
RR format: <insn> R1,R2
+--------+----+----+ | OpCode | R1 | R2 | +--------+----+----+ 0 8 12 15
RRE format: <insn> R1,R2
+------------------+--------+----+----+ | OpCode |////////| R1 | R2 | +------------------+--------+----+----+ 0 16 24 28 31
RRF format: <insn> R1,R2,R3,M4
+------------------+----+----+----+----+ | OpCode | R3 | M4 | R1 | R2 | +------------------+----+----+----+----+ 0 16 20 24 28 31
RRS format: <insn> R1,R2,M3,D4(B4)
+--------+----+----+----+-------------+----+----+--------+ | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | +--------+----+----+----+-------------+----+----+--------+ 0 8 12 16 20 32 36 40 47
RS format: <insn> R1,R3,D2(B2)
+--------+----+----+----+-------------+ | OpCode | R1 | R3 | B2 | D2 | +--------+----+----+----+-------------+ 0 8 12 16 20 31
RSE format: <insn> R1,R3,D2(B2)
+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47
RSI format: <insn> R1,R3,I2
+--------+----+----+------------------------------------+ | OpCode | R1 | R3 | I2 | +--------+----+----+------------------------------------+ 0 8 12 16 47
RSY format: <insn> R1,R3,D2(B2)
+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47
RX format: <insn> R1,D2(X2,B2)
+--------+----+----+----+-------------+ | OpCode | R1 | X2 | B2 | D2 | +--------+----+----+----+-------------+ 0 8 12 16 20 31
RXE format: <insn> R1,D2(X2,B2)
+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47
RXF format: <insn> R1,R3,D2(X2,B2)
+--------+----+----+----+-------------+----+---+--------+ | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | +--------+----+----+----+-------------+----+---+--------+ 0 8 12 16 20 32 36 40 47
RXY format: <insn> R1,D2(X2,B2)
+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 36 40 47
S format: <insn> D2(B2)
+------------------+----+-------------+ | OpCode | B2 | D2 | +------------------+----+-------------+ 0 16 20 31
SI format: <insn> D1(B1),I2
+--------+---------+----+-------------+ | OpCode | I2 | B1 | D1 | +--------+---------+----+-------------+ 0 8 16 20 31
SIY format: <insn> D1(B1),U2
+--------+---------+----+-------------+--------+--------+ | OpCode | I2 | B1 | DL1 | DH1 | OpCode | +--------+---------+----+-------------+--------+--------+ 0 8 16 20 32 36 40 47
SIL format: <insn> D1(B1),I2
+------------------+----+-------------+-----------------+ | OpCode | B1 | D1 | I2 | +------------------+----+-------------+-----------------+ 0 16 20 32 47
SS format: <insn> D1(R1,B1),D2(B3),R3
+--------+----+----+----+-------------+----+------------+ | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47
SSE format: <insn> D1(B1),D2(B2)
+------------------+----+-------------+----+------------+ | OpCode | B1 | D1 | B2 | D2 | +------------------+----+-------------+----+------------+ 0 8 12 16 20 32 36 47
SSF format: <insn> D1(B1),D2(B2),R3
+--------+----+----+----+-------------+----+------------+ | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47
For the complete list of all instruction format variants see the Principles of Operation manuals.
A specific bit pattern can have multiple mnemonics, for example
the bit pattern ‘0xa7000000’ has the mnemonics ‘tmh’ and
‘tmlh’. In addition, there are a number of mnemonics recognized by
as
that are not present in the Principles of Operation.
These are the short forms of the branch instructions, where the condition
code mask operand is encoded in the mnemonic. This is relevant for the
branch instructions, the compare and branch instructions, and the
compare and trap instructions.
For the branch instructions there are 20 condition code strings that can be used as part of the mnemonic in place of a mask operand in the instruction format:
instruction | short form
|
---|---|
bcr M1,R2 | b<m>r R2
|
bc M1,D2(X2,B2) | b<m> D2(X2,B2)
|
brc M1,I2 | j<m> I2
|
brcl M1,I2 | jg<m> I2
|
In the mnemonic for a branch instruction the condition code string <m> can be any of the following:
o | jump on overflow / if ones
|
h | jump on A high
|
p | jump on plus
|
nle | jump on not low or equal
|
l | jump on A low
|
m | jump on minus
|
nhe | jump on not high or equal
|
lh | jump on low or high
|
ne | jump on A not equal B
|
nz | jump on not zero / if not zeros
|
e | jump on A equal B
|
z | jump on zero / if zeroes
|
nlh | jump on not low or high
|
he | jump on high or equal
|
nl | jump on A not low
|
nm | jump on not minus / if not mixed
|
le | jump on low or equal
|
nh | jump on A not high
|
np | jump on not plus
|
no | jump on not overflow / if not ones
|
For the compare and branch, and compare and trap instructions there are 12 condition code strings that can be used as part of the mnemonic in place of a mask operand in the instruction format:
instruction | short form
|
---|---|
crb R1,R2,M3,D4(B4) | crb<m> R1,R2,D4(B4)
|
cgrb R1,R2,M3,D4(B4) | cgrb<m> R1,R2,D4(B4)
|
crj R1,R2,M3,I4 | crj<m> R1,R2,I4
|
cgrj R1,R2,M3,I4 | cgrj<m> R1,R2,I4
|
cib R1,I2,M3,D4(B4) | cib<m> R1,I2,D4(B4)
|
cgib R1,I2,M3,D4(B4) | cgib<m> R1,I2,D4(B4)
|
cij R1,I2,M3,I4 | cij<m> R1,I2,I4
|
cgij R1,I2,M3,I4 | cgij<m> R1,I2,I4
|
crt R1,R2,M3 | crt<m> R1,R2
|
cgrt R1,R2,M3 | cgrt<m> R1,R2
|
cit R1,I2,M3 | cit<m> R1,I2
|
cgit R1,I2,M3 | cgit<m> R1,I2
|
clrb R1,R2,M3,D4(B4) | clrb<m> R1,R2,D4(B4)
|
clgrb R1,R2,M3,D4(B4) | clgrb<m> R1,R2,D4(B4)
|
clrj R1,R2,M3,I4 | clrj<m> R1,R2,I4
|
clgrj R1,R2,M3,I4 | clgrj<m> R1,R2,I4
|
clib R1,I2,M3,D4(B4) | clib<m> R1,I2,D4(B4)
|
clgib R1,I2,M3,D4(B4) | clgib<m> R1,I2,D4(B4)
|
clij R1,I2,M3,I4 | clij<m> R1,I2,I4
|
clgij R1,I2,M3,I4 | clgij<m> R1,I2,I4
|
clrt R1,R2,M3 | clrt<m> R1,R2
|
clgrt R1,R2,M3 | clgrt<m> R1,R2
|
clfit R1,I2,M3 | clfit<m> R1,I2
|
clgit R1,I2,M3 | clgit<m> R1,I2
|
In the mnemonic for a compare and branch and compare and trap instruction the condition code string <m> can be any of the following:
h | jump on A high
|
nle | jump on not low or equal
|
l | jump on A low
|
nhe | jump on not high or equal
|
ne | jump on A not equal B
|
lh | jump on low or high
|
e | jump on A equal B
|
nlh | jump on not low or high
|
nl | jump on A not low
|
he | jump on high or equal
|
nh | jump on A not high
|
le | jump on low or equal
|
If a symbol modifier is attached to a symbol in an expression for an instruction operand field, the symbol term is replaced with a reference to an object in the global offset table (GOT) or the procedure linkage table (PLT). The following expressions are allowed: ‘symbol@modifier + constant’, ‘symbol@modifier + label + constant’, and ‘symbol@modifier - label + constant’. The term ‘symbol’ is the symbol that will be entered into the GOT or PLT, ‘label’ is a local label, and ‘constant’ is an arbitrary expression that the assembler can evaluate to a constant value.
The term ‘(symbol + constant1)@modifier +/- label + constant2’ is also accepted but a warning message is printed and the term is converted to ‘symbol@modifier +/- label + constant1 + constant2’.
@got
@got12
@gotent
@gotoff
@gotplt
@plt
@pltoff
@gotntpoff
@indntpoff
For more information about the thread local storage modifiers ‘gotntpoff’ and ‘indntpoff’ see the ELF extension documentation ‘ELF Handling For Thread-Local Storage’.
The thread local storage instruction markers are used by the linker to perform code optimization.
:tls_load
:tls_gdcall
:tls_ldcall
For more information about the thread local storage instruction marker and the linker optimizations see the ELF extension documentation ‘ELF Handling For Thread-Local Storage’.
A literal pool is a collection of values. To access the values a pointer to the literal pool is loaded to a register, the literal pool register. Usually, register %r13 is used as the literal pool register (s390 Register). Literal pool entries are created by adding the suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an instruction operand. The expression is added to the literal pool and the operand is replaced with the offset to the literal in the literal pool.
:lit1
:lit2
:lit4
:lit8
The assembler directive ‘.ltorg’ is used to emit all literal pool entries to the current position.
as
for s390 supports all of the standard ELF
assembler directives as outlined in the main part of this document.
Some directives have been extended and there are some additional
directives, which are only available for the s390 as
.
.insn
.short
.long
.quad
@got
@got12
@gotoff
@gotplt
@plt
@pltoff
@tlsgd
@tlsldm
@gotntpoff
@indntpoff
@dtpoff
@ntpoff
For more information about the thread local storage modifiers see the ELF extension documentation ‘ELF Handling For Thread-Local Storage’.
.ltorg
.machine
STRING[+
EXTENSION]...
string
may be any of the -march=
selection options, or push
, or pop
. .machine
push
saves the currently selected cpu, which may be restored with
.machine pop
. Be aware that the cpu string has to be put
into double quotes in case it contains characters not appropriate
for identifiers. So you have to write "z9-109"
instead of
just z9-109
. Extensions can be specified after the cpu
name, separated by plus characters. Valid extensions are:
htm
,
nohtm
,
vx
,
novx
.
They extend the basic instruction set with features from a higher
cpu level, or remove support for a feature from the given cpu
level.
Example: z13+nohtm
allows all instructions of the z13 cpu
except instructions from the HTM facility.
.machinemode string
string
may be esa
, zarch
,
zarch_nohighgprs
, push
, or pop
.
.machinemode zarch_nohighgprs
can be used to prevent the
highgprs
flag from being set in the ELF header of the output
file. This is useful in situations where the code is gated with a
runtime check which makes sure that the code is only executed on
kernels providing the highgprs
feature.
.machinemode push
saves the currently selected mode, which may
be restored with .machinemode pop
.
The assembler recognizes both the ieee floating-point instruction and the hexadecimal floating-point instructions. The floating-point constructors ‘.float’, ‘.single’, and ‘.double’ always emit the ieee format. To assemble hexadecimal floating-point constants the ‘.long’ and ‘.quad’ directives must be used.
The following table lists all available SCORE options.
-G
numgp
register. The default value is 8.
-EB
-EL
-FIXDD
-NWARN
-SCORE5
-SCORE5U
-SCORE7
-SCORE3
-march=score7
-march=score3
-USE_R1
-KPIC
-O0
-V
A number of assembler directives are available for SCORE. The following table is far from complete.
.set nwarn
.set fixdd
.set nofixdd
.set r1
set nor1
.sdata
.rdata
.frame "frame-register", "offset", "return-pc-register"
.mask "bitmask", "frameoffset"
.ent "proc-name"
.end proc-name
.bss
The presence of a ‘#’ appearing anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘;’ character can be used to separate statements on the same line.
as
has following command-line options for the Renesas
(formerly Hitachi) / SuperH SH family.
--little
--big
--relax
--small
--dsp
--renesas
--allow-reg-prefix
--fdpic
--isa=sh4 | sh4a
--isa=dsp
--isa=fp
--isa=all
-h-tick-hex
‘!’ is the line comment character.
You can use ‘;’ instead of a newline to separate statements.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
Since ‘$’ has no special meaning, you may use it in symbol names.
You can use the predefined symbols ‘r0’, ‘r1’, ‘r2’, ‘r3’, ‘r4’, ‘r5’, ‘r6’, ‘r7’, ‘r8’, ‘r9’, ‘r10’, ‘r11’, ‘r12’, ‘r13’, ‘r14’, and ‘r15’ to refer to the SH registers.
The SH also has these control registers:
pr
pc
mach
macl
sr
gbr
vbr
as
understands the following addressing modes for the SH.
R
n in the following refers to any of the numbered
registers, but not the control registers.
R
n@R
n@-R
n@R
n+
@(
disp, R
n)
@(R0, R
n)
@(
disp, GBR)
GBR
offset
@(R0, GBR)
@(
disp, PC)
as
implementation allows you to use the simpler form
addr anywhere a PC relative address is called for; the alternate
form is supported for compatibility with other assemblers.
#
immSH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
SH groups can use .float
directive to generate ieee
floating-point numbers.
SH2E and SH3E support single-precision floating point calculations as well as entirely PCAPI compatible emulation of double-precision floating point calculations. SH2E and SH3E instructions are a subset of the floating point calculations conforming to the IEEE754 standard.
In addition to single-precision and double-precision floating-point operation capability, the on-chip FPU of SH4 has a 128-bit graphic engine that enables 32-bit floating-point data to be processed 128 bits at a time. It also supports 4 * 4 array operations and inner product operations. Also, a superscalar architecture is employed that enables simultaneous execution of two instructions (including FPU instructions), providing performance of up to twice that of conventional architectures at the same frequency.
uaword
ualong
uaquad
as
will issue a warning when a misaligned .word
,
.long
, or .quad
directive is used. You may use
.uaword
, .ualong
, or .uaquad
to indicate that the
value is intentionally misaligned.
For detailed information on the SH machine instruction set, see SH-Microcomputer User's Manual (Renesas) or SH-4 32-bit CPU Core Architecture (SuperH) and SuperH (SH) 64-Bit RISC Series (SuperH).
as
implements all the standard SH opcodes. No additional
pseudo-instructions are needed on this family. Note, however, that
because as
supports a simpler form of PC-relative
addressing, you may simply write (for example)
mov.l bar,r0
where other assemblers might require an explicit displacement to
bar
from the program counter:
mov.l @(disp, PC)
The SPARC chip family includes several successive versions, using the same core instruction set, but including a few additional instructions at each version. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.
By default, as
assumes the core instruction set (SPARC
v6), but “bumps” the architecture level as needed: it switches to
successively higher architectures as it encounters instructions that
only exist in the higher levels.
If not configured for SPARC v9 (sparc64-*-*
) GAS will not bump
past sparclite by default, an option must be passed to enable the
v9 instructions.
GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite.
-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |
-Av8plusv | -Av8plusm | -Av8plusm8
-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8
-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
-Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6
as
reports a fatal error if it encounters an instruction
or feature requiring an incompatible or higher level.
‘-Av8plus’, ‘-Av8plusa’, ‘-Av8plusb’, ‘-Av8plusc’, ‘-Av8plusd’, and ‘-Av8plusv’ select a 32 bit environment.
‘-Av9’, ‘-Av9a’, ‘-Av9b’, ‘-Av9c’, ‘-Av9d’, ‘-Av9e’, ‘-Av9v’ and ‘-Av9m’ select a 64 bit environment and are not available unless GAS is explicitly configured with 64 bit environment support.
‘-Av8plusa’ and ‘-Av9a’ enable the SPARC V9 instruction set with UltraSPARC VIS 1.0 extensions.
‘-Av8plusb’ and ‘-Av9b’ enable the UltraSPARC VIS 2.0 instructions, as well as the instructions enabled by ‘-Av8plusa’ and ‘-Av9a’.
‘-Av8plusc’ and ‘-Av9c’ enable the UltraSPARC Niagara instructions, as well as the instructions enabled by ‘-Av8plusb’ and ‘-Av9b’.
‘-Av8plusd’ and ‘-Av9d’ enable the floating point fused multiply-add, VIS 3.0, and HPC extension instructions, as well as the instructions enabled by ‘-Av8plusc’ and ‘-Av9c’.
‘-Av8pluse’ and ‘-Av9e’ enable the cryptographic instructions, as well as the instructions enabled by ‘-Av8plusd’ and ‘-Av9d’.
‘-Av8plusv’ and ‘-Av9v’ enable floating point unfused multiply-add, and integer multiply-add, as well as the instructions enabled by ‘-Av8pluse’ and ‘-Av9e’.
‘-Av8plusm’ and ‘-Av9m’ enable the VIS 4.0, subtract extended, xmpmul, xmontmul and xmontsqr instructions, as well as the instructions enabled by ‘-Av8plusv’ and ‘-Av9v’.
‘-Av8plusm8’ and ‘-Av9m8’ enable the instructions introduced in the Oracle SPARC Architecture 2017 and the M8 processor, as well as the instructions enabled by ‘-Av8plusm’ and ‘-Av9m’.
‘-Asparc’ specifies a v9 environment. It is equivalent to ‘-Av9’ if the word size is 64-bit, and ‘-Av8plus’ otherwise.
‘-Asparcvis’ specifies a v9a environment. It is equivalent to ‘-Av9a’ if the word size is 64-bit, and ‘-Av8plusa’ otherwise.
‘-Asparcvis2’ specifies a v9b environment. It is equivalent to ‘-Av9b’ if the word size is 64-bit, and ‘-Av8plusb’ otherwise.
‘-Asparcfmaf’ specifies a v9b environment with the floating point fused multiply-add instructions enabled.
‘-Asparcima’ specifies a v9b environment with the integer multiply-add instructions enabled.
‘-Asparcvis3’ specifies a v9b environment with the VIS 3.0, HPC , and floating point fused multiply-add instructions enabled.
‘-Asparcvis3r’ specifies a v9b environment with the VIS 3.0, HPC, and floating point unfused multiply-add instructions enabled.
‘-Asparc5’ is equivalent to ‘-Av9m’.
‘-Asparc6’ is equivalent to ‘-Av9m8’.
-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |
-xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b
-xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v
-xarch=v9m | -xarch=v9m8
-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
-xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6
-bump
-32 | -64
--dcti-couples-detect
SPARC GAS normally permits data to be misaligned. For example, it
permits the .long
pseudo-op to be used on a byte boundary.
However, the native SunOS assemblers issue an error when they see
misaligned data.
You can use the --enforce-aligned-data
option to make SPARC GAS
also issue an error about misaligned data, just as the SunOS
assemblers do.
The --enforce-aligned-data
option is not the default because gcc
issues misaligned data pseudo-ops when it initializes certain packed
data structures (structures defined using the packed
attribute).
You may have to assemble with GAS in order to initialize packed data
structures in your own code.
The assembler syntax closely follows The Sparc Architecture Manual, versions 8 and 9, as well as most extensions defined by Sun for their UltraSPARC and Niagara line of processors.
A ‘!’ character appearing anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
‘;’ can be used instead of a newline to separate statements.
The Sparc integer register file is broken down into global, outgoing, local, and incoming.
Floating point registers are simply referred to as ‘%fn’. When assembling for pre-V9, only 32 floating point registers are available. For V9 and later there are 64, but there are restrictions when referencing the upper 32 registers. They can only be accessed as double or quad, and thus only even or quad numbered accesses are allowed. For example, ‘%f34’ is a legal floating point register, but ‘%f35’ is not.
Floating point registers accessed as double can also be referred using the ‘%dn’ notation, where n is even. Similarly, floating point registers accessed as quad can be referred using the ‘%qn’ notation, where n is a multiple of 4. For example, ‘%f4’ can be denoted as both ‘%d4’ and ‘%q4’. On the other hand, ‘%f2’ can be denoted as ‘%d2’ but not as ‘%q2’.
Certain V9 instructions allow access to ancillary state registers. Most simply they can be referred to as ‘%asrn’ where n can be from 16 to 31. However, there are some aliases defined to reference ASR registers defined for various UltraSPARC processors:
Various V9 branch and conditional move instructions allow specification of which set of integer condition codes to test. These are referred to as ‘%xcc’ and ‘%icc’.
Additionally, GAS supports the so-called “natural” condition codes; these are referred to as ‘%ncc’ and reference to ‘%icc’ if the word size is 32, ‘%xcc’ if the word size is 64.
In V9, there are 4 sets of floating point condition codes which are referred to as ‘%fccn’.
Several special privileged and non-privileged registers exist:
Several special register names exist for hypervisor mode code:
Several Sparc instructions take an immediate operand field for which mnemonic names exist. Two such examples are ‘membar’ and ‘prefetch’. Another example are the set of V9 memory access instruction that allow specification of an address space identifier.
The ‘membar’ instruction specifies a memory barrier that is the defined by the operand which is a bitmask. The supported mask mnemonics are:
membar
must have
been performed and the effects of any exceptions become visible before
any instructions after the membar
may be initiated. This
corresponds to membar
cmask field bit 2.
membar
must have been performed before
any memory operation after the membar
may be initiated. This
corresponds to membar
cmask field bit 1.
membar
must complete before any load following the
membar
referencing the same address can be initiated. This
corresponds to membar
cmask field bit 0.
membar
instruction must be visible to all
processors before the effect of any stores following the
membar
. Equivalent to the deprecated stbar
instruction.
This corresponds to membar
mmask field bit 3.
membar
instruction must have been performed before the effect
of any stores following the membar
is visible to any other
processor. This corresponds to membar
mmask field bit 2.
membar
instruction must be visible to all
processors before loads following the membar
may be performed.
This corresponds to membar
mmask field bit 1.
membar
instruction must have been performed before any loads
following the membar
may be performed. This corresponds to
membar
mmask field bit 0.
These values can be ored together, for example:
membar #Sync membar #StoreLoad | #LoadLoad membar #StoreLoad | #StoreStore
The prefetch
and prefetcha
instructions take a prefetch
function code. The following prefetch function code constant
mnemonics are available:
‘#one_read’ requests a prefetch for one read, and corresponds to a prefetch function code of 1.
‘#n_writes’ requests a prefetch for several writes (and possibly reads), and corresponds to a prefetch function code of 2.
‘#one_write’ requests a prefetch for one write, and corresponds to a prefetch function code of 3.
‘#page’ requests a prefetch page, and corresponds to a prefetch function code of 4.
‘#invalidate’ requests a prefetch invalidate, and corresponds to a prefetch function code of 16.
‘#unified’ requests a prefetch to the nearest unified cache, and corresponds to a prefetch function code of 17.
‘#n_reads_strong’ requests a strong prefetch for several reads, and corresponds to a prefetch function code of 20.
‘#one_read_strong’ requests a strong prefetch for one read, and corresponds to a prefetch function code of 21.
‘#n_writes_strong’ requests a strong prefetch for several writes, and corresponds to a prefetch function code of 22.
‘#one_write_strong’ requests a strong prefetch for one write, and corresponds to a prefetch function code of 23.
Onle one prefetch code may be specified. Here are some examples:
prefetch [%l0 + %l2], #one_read prefetch [%g2 + 8], #n_writes prefetcha [%g1] 0x8, #unified prefetcha [%o0 + 0x10] %asi, #n_reads
The actual behavior of a given prefetch function code is processor specific. If a processor does not implement a given prefetch function code, it will treat the prefetch instruction as a nop.
For instructions that accept an immediate address space identifier,
as
provides many mnemonics corresponding to
V9 defined as well as UltraSPARC and Niagara extended values.
For example, ‘#ASI_P’ and ‘#ASI_BLK_INIT_QUAD_LDD_AIUS’.
See the V9 and processor specific manuals for details.
ELF relocations are available as defined in the 32-bit and 64-bit Sparc ELF specifications.
R_SPARC_HI22
is obtained using ‘%hi’ and R_SPARC_LO10
is obtained using ‘%lo’. Likewise R_SPARC_HIX22
is
obtained from ‘%hix’ and R_SPARC_LOX10
is obtained
using ‘%lox’. For example:
sethi %hi(symbol), %g1 or %g1, %lo(symbol), %g1 sethi %hix(symbol), %g1 xor %g1, %lox(symbol), %g1
These “high” mnemonics extract bits 31:10 of their operand, and the “low” mnemonics extract bits 9:0 of their operand.
V9 code model relocations can be requested as follows:
R_SPARC_HH22
is requested using ‘%hh’. It can
also be generated using ‘%uhi’.
R_SPARC_HM10
is requested using ‘%hm’. It can
also be generated using ‘%ulo’.
R_SPARC_LM22
is requested using ‘%lm’.
R_SPARC_H44
is requested using ‘%h44’.
R_SPARC_M44
is requested using ‘%m44’.
R_SPARC_L44
is requested using ‘%l44’ or ‘%l34’.
R_SPARC_H34
is requested using ‘%h34’.
The ‘%l34’ generates a R_SPARC_L44
relocation because it
calculates the necessary value, and therefore no explicit
R_SPARC_L34
relocation needed to be created for this purpose.
The ‘%h34’ and ‘%l34’ relocations are used for the abs34 code model. Here is an example abs34 address generation sequence:
sethi %h34(symbol), %g1 sllx %g1, 2, %g1 or %g1, %l34(symbol), %g1
The PC relative relocation R_SPARC_PC22
can be obtained by
enclosing an operand inside of ‘%pc22’. Likewise, the
R_SPARC_PC10
relocation can be obtained using ‘%pc10’.
These are mostly used when assembling PIC code. For example, the
standard PIC sequence on Sparc to get the base of the global offset
table, PC relative, into a register, can be performed as:
sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
Several relocations exist to allow the link editor to potentially
optimize GOT data references. The R_SPARC_GOTDATA_OP_HIX22
relocation can obtained by enclosing an operand inside of
‘%gdop_hix22’. The R_SPARC_GOTDATA_OP_LOX10
relocation can obtained by enclosing an operand inside of
‘%gdop_lox10’. Likewise, R_SPARC_GOTDATA_OP
can be
obtained by enclosing an operand inside of ‘%gdop’.
For example, assuming the GOT base is in register %l7
:
sethi %gdop_hix22(symbol), %l1 xor %l1, %gdop_lox10(symbol), %l1 ld [%l7 + %l1], %l2, %gdop(symbol)
There are many relocations that can be requested for access to thread local storage variables. All of the Sparc TLS mnemonics are supported:
R_SPARC_TLS_GD_HI22
is requested using ‘%tgd_hi22’.
R_SPARC_TLS_GD_LO10
is requested using ‘%tgd_lo10’.
R_SPARC_TLS_GD_ADD
is requested using ‘%tgd_add’.
R_SPARC_TLS_GD_CALL
is requested using ‘%tgd_call’.
R_SPARC_TLS_LDM_HI22
is requested using ‘%tldm_hi22’.
R_SPARC_TLS_LDM_LO10
is requested using ‘%tldm_lo10’.
R_SPARC_TLS_LDM_ADD
is requested using ‘%tldm_add’.
R_SPARC_TLS_LDM_CALL
is requested using ‘%tldm_call’.
R_SPARC_TLS_LDO_HIX22
is requested using ‘%tldo_hix22’.
R_SPARC_TLS_LDO_LOX10
is requested using ‘%tldo_lox10’.
R_SPARC_TLS_LDO_ADD
is requested using ‘%tldo_add’.
R_SPARC_TLS_IE_HI22
is requested using ‘%tie_hi22’.
R_SPARC_TLS_IE_LO10
is requested using ‘%tie_lo10’.
R_SPARC_TLS_IE_LD
is requested using ‘%tie_ld’.
R_SPARC_TLS_IE_LDX
is requested using ‘%tie_ldx’.
R_SPARC_TLS_IE_ADD
is requested using ‘%tie_add’.
R_SPARC_TLS_LE_HIX22
is requested using ‘%tle_hix22’.
R_SPARC_TLS_LE_LOX10
is requested using ‘%tle_lox10’.
Here are some example TLS model sequences.
First, General Dynamic:
sethi %tgd_hi22(symbol), %l1 add %l1, %tgd_lo10(symbol), %l1 add %l7, %l1, %o0, %tgd_add(symbol) call __tls_get_addr, %tgd_call(symbol) nop
Local Dynamic:
sethi %tldm_hi22(symbol), %l1 add %l1, %tldm_lo10(symbol), %l1 add %l7, %l1, %o0, %tldm_add(symbol) call __tls_get_addr, %tldm_call(symbol) nop sethi %tldo_hix22(symbol), %l1 xor %l1, %tldo_lox10(symbol), %l1 add %o0, %l1, %l1, %tldo_add(symbol)
Initial Exec:
sethi %tie_hi22(symbol), %l1 add %l1, %tie_lo10(symbol), %l1 ld [%l7 + %l1], %o0, %tie_ld(symbol) add %g7, %o0, %o0, %tie_add(symbol) sethi %tie_hi22(symbol), %l1 add %l1, %tie_lo10(symbol), %l1 ldx [%l7 + %l1], %o0, %tie_ldx(symbol) add %g7, %o0, %o0, %tie_add(symbol)
And finally, Local Exec:
sethi %tle_hix22(symbol), %l1 add %l1, %tle_lox10(symbol), %l1 add %g7, %l1, %l1
When assembling for 64-bit, and a secondary constant addend is
specified in an address expression that would normally generate
an R_SPARC_LO10
relocation, the assembler will emit an
R_SPARC_OLO10
instead.
Often it is desirable to write code in an operand size agnostic
manner. as
provides support for this via
operand size opcode translations. Translations are supported
for loads, stores, shifts, compare-and-swap atomics, and the
‘clr’ synthetic instruction.
If generating 32-bit code, as
will generate the
32-bit opcode. Whereas if 64-bit code is being generated,
the 64-bit opcode will be emitted. For example ldn
will be transformed into ld
for 32-bit code and
ldx
for 64-bit code.
Here is an example meant to demonstrate all the supported opcode translations:
ldn [%o0], %o1 ldna [%o0] %asi, %o2 stn %o1, [%o0] stna %o2, [%o0] %asi slln %o3, 3, %o3 srln %o4, 8, %o4 sran %o5, 12, %o5 casn [%o0], %o1, %o2 casna [%o0] %asi, %o1, %o2 clrn %g1
In 32-bit mode as
will emit:
ld [%o0], %o1 lda [%o0] %asi, %o2 st %o1, [%o0] sta %o2, [%o0] %asi sll %o3, 3, %o3 srl %o4, 8, %o4 sra %o5, 12, %o5 cas [%o0], %o1, %o2 casa [%o0] %asi, %o1, %o2 clr %g1
And in 64-bit mode as
will emit:
ldx [%o0], %o1 ldxa [%o0] %asi, %o2 stx %o1, [%o0] stxa %o2, [%o0] %asi sllx %o3, 3, %o3 srlx %o4, 8, %o4 srax %o5, 12, %o5 casx [%o0], %o1, %o2 casxa [%o0] %asi, %o1, %o2 clrx %g1
Finally, the ‘.nword’ translating directive is supported as well. It is documented in the section on Sparc machine directives.
The Sparc uses ieee floating-point numbers.
The Sparc version of as
supports the following additional
machine directives:
.align
.common
"bss"
. This behaves somewhat like .comm
, but the
syntax is different.
.half
.short
.
.nword
.nword
directive produces native word sized value,
ie. if assembling with -32 it is equivalent to .word
, if assembling
with -64 it is equivalent to .xword
.
.proc
.register
#scratch
,
it is a scratch register, if it is #ignore
, it just suppresses any
errors about using undeclared global register, but does not emit any
information about it into the object file. This can be useful e.g. if you
save the register before use and restore it after.
.reserve
"bss"
. This behaves somewhat like .lcomm
, but the
syntax is different.
.seg
"text"
, "data"
, or
"data1"
. It behaves like .text
, .data
, or
.data 1
.
.skip
.space
directive.
.word
.word
directive produces 32 bit values,
instead of the 16 bit values it produces on many other machines.
.xword
.xword
directive produces
64 bit values.
The TMS320C54X version of as
has a few machine-dependent options.
You can use the ‘-mfar-mode’ option to enable extended addressing mode. All addresses will be assumed to be > 16 bits, and the appropriate relocation types will be used. This option is equivalent to using the ‘.far_mode’ directive in the assembly code. If you do not use the ‘-mfar-mode’ option, all references will be assumed to be 16 bits. This option may be abbreviated to ‘-mf’.
You can use the ‘-mcpu’ option to specify a particular CPU.
This option is equivalent to using the ‘.version’ directive in the
assembly code. For recognized CPU codes, see
See .version
. The default CPU version is
‘542’.
You can use the ‘-merrors-to-file’ option to redirect error output to a file (this provided for those deficient environments which don't provide adequate output redirection). This option may be abbreviated to ‘-me’.
A blocked section or memory block is guaranteed not to cross the blocking boundary (usually a page, or 128 words) if it is smaller than the blocking size, or to start on a page boundary if it is larger than the blocking size.
‘C54XDSP_DIR’ and ‘A_DIR’ are semicolon-separated paths which are added to the list of directories normally searched for source and include files. ‘C54XDSP_DIR’ will override ‘A_DIR’.
The TIC54X version of as
allows the following additional
constant formats, using a suffix to indicate the radix:
Binary000000B, 011000b
Octal10Q, 224q
Hexadecimal45h, 0FH
A subset of allowable symbols (which we'll call subsyms) may be assigned
arbitrary string values. This is roughly equivalent to C preprocessor
#define macros. When as
encounters one of these
symbols, the symbol is replaced in the input stream by its string value.
Subsym names must begin with a letter.
Subsyms may be defined using the .asg
and .eval
directives
(See .asg
,
See .eval
.
Expansion is recursive until a previously encountered symbol is seen, at which point substitution stops.
In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, and SYM1 is replaced with x. At this point, x has already been encountered and the substitution stops.
.asg "x",SYM1 .asg "SYM1",SYM2 .asg "SYM2",x add x,a ; final code assembled is "add x, a"
Macro parameters are converted to subsyms; a side effect of this is the normal
as
'\ARG' dereferencing syntax is unnecessary. Subsyms
defined within a macro will have global scope, unless the .var
directive is used to identify the subsym as a local macro variable
see .var
.
Substitution may be forced in situations where replacement might be ambiguous by placing colons on either side of the subsym. The following code:
.eval "10",x LAB:X: add #x, a
When assembled becomes:
LAB10 add #10, a
Smaller parts of the string assigned to a subsym may be accessed with the following syntax:
:
symbol(
char_index):
:
symbol(
start,
length):
Local labels may be defined in two ways:
Local labels thus defined may be redefined or automatically generated. The scope of a local label is based on when it may be undefined or reset. This happens when one of the following situations is encountered:
.newblock
The following built-in functions may be used to generate a floating-point value. All return a floating-point value except ‘$cvi’, ‘$int’, and ‘$sgn’, which return an integer value.
$acos(
expr)
$asin(
expr)
$atan(
expr)
$atan2(
expr1,
expr2)
$ceil(
expr)
$cosh(
expr)
$cos(
expr)
$cvf(
expr)
$cvi(
expr)
$exp(
expr)
$fabs(
expr)
$floor(
expr)
$fmod(
expr1,
expr2)
$int(
expr)
$ldexp(
expr1,
expr2)
$log10(
expr)
$log(
expr)
$max(
expr1,
expr2)
$min(
expr1,
expr2)
$pow(
expr1,
expr2)
$round(
expr)
$sgn(
expr)
$sin(
expr)
$sinh(
expr)
$sqrt(
expr)
$tan(
expr)
$tanh(
expr)
$trunc(
expr)
The LDX
pseudo-op is provided for loading the extended addressing bits
of a label or address. For example, if an address _label
resides
in extended program memory, the value of _label
may be loaded as
follows:
ldx #_label,16,a ; loads extended bits of _label or #_label,a ; loads lower 16 bits of _label bacc a ; full address is in accumulator A
.align [
size]
.even
.even
is
equivalent to .align
with a size of 2.
1
2
128
.asg
string,
name.eval
string,
name.bss
symbol,
size [, [
blocking_flag] [,
alignment_flag]]
.byte
value [,...,
value_n]
.ubyte
value [,...,
value_n]
.char
value [,...,
value_n]
.uchar
value [,...,
value_n]
.clink ["
section_name"]
.c_mode
.copy "
filename" |
filename.include "
filename" |
filename.data
.double
value [,...,
value_n]
.ldouble
value [,...,
value_n]
.float
value [,...,
value_n]
.xfloat
value [,...,
value_n]
.xfloat
align the result on a longword boundary. Values are
stored most-significant word first.
.drlist
.drnolist
.emsg
string.mmsg
string.wmsg
string.far_mode
-mfar-mode
.
.fclist
.fcnolist
.field
value [,
size]
.field
directives will
pack starting at the current word, filling the most significant bits
first, and aligning to the start of the next word if the field size does
not fit into the space remaining in the current word. A .align
directive with an operand of 1 will force the next .field
directive to begin packing into a new word. If a label is used, it
points to the word that contains the specified field.
.global
symbol [,...,
symbol_n]
.def
symbol [,...,
symbol_n]
.ref
symbol [,...,
symbol_n]
.def
nominally identifies a symbol defined in the current file
and available to other files. .ref
identifies a symbol used in
the current file but defined elsewhere. Both map to the standard
.global
directive.
.half
value [,...,
value_n]
.uhalf
value [,...,
value_n]
.short
value [,...,
value_n]
.ushort
value [,...,
value_n]
.int
value [,...,
value_n]
.uint
value [,...,
value_n]
.word
value [,...,
value_n]
.uword
value [,...,
value_n]
.label
symbol.length
.width
.list
.nolist
.long
value [,...,
value_n]
.ulong
value [,...,
value_n]
.xlong
value [,...,
value_n]
.long
and
.ulong
align the result on a longword boundary; xlong
does
not.
.loop [
count]
.break [
condition]
.endloop
.loop
begins the block, and
.endloop
marks its termination. count defaults to 1024,
and indicates the number of times the block should be repeated.
.break
terminates the loop so that assembly begins after the
.endloop
directive. The optional condition will cause the
loop to terminate only if it evaluates to zero.
.macro [
param1][,...
param_n]
[.mexit]
.endm
.mlib "
filename" |
filename.mlist
.mnolist
.mmregs
.set
directives for each register with
its memory-mapped value, but in reality is provided only for
compatibility and does nothing.
.newblock
as
local labels are unaffected.
.option
option_list.sblock "
section_name" |
section_name [,"
name_n" |
name_n]
.sect "
section_name"
.set "
value"
.equ "
value"
.space
size_in_bits.bes
size_in_bits.space
, it points to the
first word reserved. With .bes
, the label points to the
last word reserved.
.sslist
.ssnolist
.string "
string" [,...,"
string_n"]
.pstring "
string" [,...,"
string_n"]
.string
zero-fills the upper 8 bits of each word, while
.pstring
puts two characters into each word, filling the
most-significant bits first. Unused space is zero-filled. If a label
is used, it points to the first word initialized.
[
stag] .struct [
offset]
[
name_1] element [
count_1]
[
name_2] element [
count_2]
[
tname] .tag
stagx [
tcount]
...
[
name_n] element [
count_n]
[
ssize] .endstruct
.tag [
stag]
element
were an array. element
may be one of
.byte
, .word
, .long
, .float
, or any
equivalent of those, and the structure offset is adjusted accordingly.
.field
and .string
are also allowed; the size of
.field
is one bit, and .string
is considered to be one
word in size. Only element descriptors, structure/union tags,
.align
and conditional assembly directives are allowed within
.struct
/.endstruct
. .align
aligns member offsets
to word boundaries only. ssize, if provided, will always be
assigned the size of the structure.
The .tag
directive, in addition to being used to define a
structure/union element within a structure, may be used to apply a
structure to a symbol. Once applied to label, the individual
structure elements may be applied to label to produce the desired
offsets using label as the structure base.
.tab
[
utag] .union
[
name_1] element [
count_1]
[
name_2] element [
count_2]
[
tname] .tag
utagx[,
tcount]
...
[
name_n] element [
count_n]
[
usize] .endstruct
.tag [
utag]
.struct
, but the offset after each element is reset to
zero, and the usize is set to the maximum of all defined elements.
Starting offset for the union is always zero.
[
symbol] .usect "
section_name",
size, [,[
blocking_flag] [,
alignment_flag]]
.usect
allows definitions sections independent of .bss.
symbol points to the first location reserved by this allocation.
The symbol may be used as a variable name. size is the allocated
size in words. blocking_flag indicates whether to block this
section on a page boundary (128 words) (see TIC54X-Block).
alignment flag indicates whether the section should be
longword-aligned.
.var
sym[,...,
sym_n]
.version
version541
542
543
545
545LP
546LP
548
549
Macros do not require explicit dereferencing of arguments (i.e., \ARG).
During macro expansion, the macro parameters are converted to subsyms. If the number of arguments passed the macro invocation exceeds the number of parameters defined, the last parameter is assigned the string equivalent of all remaining arguments. If fewer arguments are given than parameters, the missing parameters are assigned empty strings. To include a comma in an argument, you must enclose the argument in quotes.
The following built-in subsym functions allow examination of the string value of subsyms (or ordinary strings). The arguments are strings unless otherwise indicated (subsyms passed as args will be replaced by the strings they represent).
$symlen(
str)
$symcmp(
str1,
str2)
$firstch(
str,
ch)
$lastch(
str,
ch)
$isdefed(
symbol)
$ismember(
symbol,
list)
$iscons(
expr)
$isname(
name)
$isreg(
reg)
$structsz(
stag)
$structacc(
stag)
The following symbols are recognized as memory-mapped registers:
The presence of a ‘;’ appearing anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The presence of an asterisk (‘*’) at the start of a line also indicates a comment that extends to the end of that line.
The TIC54X assembler does not currently support a line separator character.
-march=
archThe following values of arch are accepted: c62x
,
c64x
, c64x+
, c67x
, c67x+
, c674x
.
-mdsbt
-mno-dsbt
Tag_ABI_DSBT
attribute with a value of 1, indicating that the
code is using DSBT addressing. The -mno-dsbt option, the
default, causes the tag to have a value of 0, indicating that the code
does not use DSBT addressing. The linker will emit a warning if
objects of different type (DSBT and non-DSBT) are linked together.
-mpid=no
-mpid=near
-mpid=far
Tag_ABI_PID
attribute with a value indicating the form of data
addressing used by the code. -mpid=no, the default,
indicates position-dependent data addressing, -mpid=near
indicates position-independent addressing with GOT accesses using near
DP addressing, and -mpid=far indicates position-independent
addressing with GOT accesses using far DP addressing. The linker will
emit a warning if objects built with different settings of this option
are linked together.
-mpic
-mno-pic
Tag_ABI_PIC
attribute with a value of 1, indicating that the
code is using position-independent code addressing, The
-mno-pic
option, the default, causes the tag to have a value of
0, indicating position-dependent code addressing. The linker will
emit a warning if objects of different type (position-dependent and
position-independent) are linked together.
-mbig-endian
-mlittle-endian
The presence of a ‘;’ on a line indicates the start of a comment that extends to the end of the current line. If a ‘#’ or ‘*’ appears as the first character of a line, the whole line is treated as a comment. Note that if a line starts with a ‘#’ character then it can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘@’ character can be used instead of a newline to separate statements.
Instruction, register and functional unit names are case-insensitive. as requires fully-specified functional unit names, such as ‘.S1’, ‘.L1X’ or ‘.D1T2’, on all instructions using a functional unit.
For some instructions, there may be syntactic ambiguity between register or functional unit names and the names of labels or other symbols. To avoid this, enclose the ambiguous symbol name in parentheses; register and functional unit names may not be enclosed in parentheses.
Directives controlling the set of instructions accepted by the assembler have effect for instructions between the directive and any subsequent directive overriding it.
.arch
arch.cantunwind
If this is not specified then frame unwinding information will be constructed from CFI directives. see CFI directives.
.c6xabi_attribute
tag,
valueThe tag is either an attribute number or one of
Tag_ISA
, Tag_ABI_wchar_t
,
Tag_ABI_stack_align_needed
,
Tag_ABI_stack_align_preserved
, Tag_ABI_DSBT
,
Tag_ABI_PID
, Tag_ABI_PIC
,
TAG_ABI_array_object_alignment
,
TAG_ABI_array_object_align_expected
,
Tag_ABI_compatibility
and Tag_ABI_conformance
. The
value is either a number
, "string"
, or
number, "string"
depending on the tag.
.ehtype
symbol.endp
.handlerdata
directive then this also switched back to the previous
text section.
.handlerdata
.endp
directive will be added to the exception table entry.
Must be preceded by a CFI block containing a .cfi_lsda
directive.
.nocmp
.personalityindex
index.personality
name.scomm
symbol,
size,
align.comm
, creating a common symbol symbol with size size
and alignment align, but unlike when using .comm
, this symbol
will be placed into the small BSS section by the linker.
The following table lists all available TILE-Gx specific options:
-m32 | -m64
-EB | -EL
Block comments are delimited by ‘/*’ and ‘*/’. End of line comments may be introduced by ‘#’.
Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma-separated list of operands:
opcode [operand, ...]
Instructions must be separated by a newline or semicolon.
There are two ways to write code: either write naked instructions, which the assembler is free to combine into VLIW bundles, or specify the VLIW bundles explicitly.
Bundles are specified using curly braces:
{ add r3,r4,r5 ; add r7,r8,r9 ; lw r10,r11 }
A bundle can span multiple lines. If you want to put multiple instructions on a line, whether in a bundle or not, you need to separate them with semicolons as in this example.
A bundle may contain one or more instructions, up to the limit
specified by the ISA (currently three). If fewer instructions are
specified than the hardware supports in a bundle, the assembler
inserts fnop
instructions automatically.
The assembler will prefer to preserve the ordering of instructions
within the bundle, putting the first instruction in a lower-numbered
pipeline than the next one, etc. This fact, combined with the
optional use of explicit fnop
or nop
instructions,
allows precise control over which pipeline executes each instruction.
If the instructions cannot be bundled in the listed order, the assembler will automatically try to find a valid pipeline assignment. If there is no way to bundle the instructions together, the assembler reports an error.
The assembler does not yet auto-bundle (automatically combine multiple
instructions into one bundle), but it reserves the right to do so in
the future. If you want to force an instruction to run by itself, put
it in a bundle explicitly with curly braces and use nop
instructions (not fnop
) to fill the remaining pipeline slots in
that bundle.
For a complete list of opcodes and descriptions of their semantics, see TILE-Gx Instruction Set Architecture, available upon request at www.tilera.com.
General-purpose registers are represented by predefined symbols of the
form ‘rN’, where N represents a number between
0
and 63
. However, the following registers have
canonical names that must be used instead:
r54
r55
r56
r57
r58
r59
r60
r61
r62
r63
The assembler will emit a warning if a numeric name is used instead of
the non-numeric name. The .no_require_canonical_reg_names
assembler pseudo-op turns off this
warning. .require_canonical_reg_names
turns it back on.
The assembler supports several modifiers when using symbol addresses in TILE-Gx instruction operands. The general syntax is the following:
modifier(symbol)
The following modifiers are supported:
hw0
hw1
hw2
hw3
hw0_last
hw0
, but it also checks
that the value does not overflow.
hw1_last
hw1
, but it also checks
that the value does not overflow.
hw2_last
hw2
, but it also checks
that the value does not overflow.
A 48-bit symbolic value is constructed by using the following idiom:
moveli r0, hw2_last(sym) shl16insli r0, r0, hw1(sym) shl16insli r0, r0, hw0(sym)
hw0_got
hw0_last_got
hw0_got
, but it also
checks that the value does not overflow.
hw1_last_got
plt
hw0_plt
hw1_plt
hw1_last_plt
hw1_plt
, but it also
checks that the value does not overflow.
hw2_last_plt
hw0_tls_gd
hw0_last_tls_gd
hw0_tls_gd
, but it also
checks that the value does not overflow.
hw1_last_tls_gd
hw0_tls_ie
hw0_last_tls_ie
hw0_tls_ie
, but it also
checks that the value does not overflow.
hw1_last_tls_ie
hw0_tls_le
hw0_last_tls_le
hw0_tls_le
, but it also
checks that the value does not overflow.
hw1_last_tls_le
tls_gd_call
tls_gd_add
tls_ie_load
.align
expression [,
expression]
.allow_suspicious_bundles
.no_allow_suspicious_bundles
.require_canonical_reg_names
.no_require_canonical_reg_names
as
has no machine-dependent command-line options for
TILEPro.
Block comments are delimited by ‘/*’ and ‘*/’. End of line comments may be introduced by ‘#’.
Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma-separated list of operands:
opcode [operand, ...]
Instructions must be separated by a newline or semicolon.
There are two ways to write code: either write naked instructions, which the assembler is free to combine into VLIW bundles, or specify the VLIW bundles explicitly.
Bundles are specified using curly braces:
{ add r3,r4,r5 ; add r7,r8,r9 ; lw r10,r11 }
A bundle can span multiple lines. If you want to put multiple instructions on a line, whether in a bundle or not, you need to separate them with semicolons as in this example.
A bundle may contain one or more instructions, up to the limit
specified by the ISA (currently three). If fewer instructions are
specified than the hardware supports in a bundle, the assembler
inserts fnop
instructions automatically.
The assembler will prefer to preserve the ordering of instructions
within the bundle, putting the first instruction in a lower-numbered
pipeline than the next one, etc. This fact, combined with the
optional use of explicit fnop
or nop
instructions,
allows precise control over which pipeline executes each instruction.
If the instructions cannot be bundled in the listed order, the assembler will automatically try to find a valid pipeline assignment. If there is no way to bundle the instructions together, the assembler reports an error.
The assembler does not yet auto-bundle (automatically combine multiple
instructions into one bundle), but it reserves the right to do so in
the future. If you want to force an instruction to run by itself, put
it in a bundle explicitly with curly braces and use nop
instructions (not fnop
) to fill the remaining pipeline slots in
that bundle.
For a complete list of opcodes and descriptions of their semantics, see TILE Processor User Architecture Manual, available upon request at www.tilera.com.
General-purpose registers are represented by predefined symbols of the
form ‘rN’, where N represents a number between
0
and 63
. However, the following registers have
canonical names that must be used instead:
r54
r55
r56
r57
r58
r59
r60
r61
r62
r63
The assembler will emit a warning if a numeric name is used instead of
the canonical name. The .no_require_canonical_reg_names
assembler pseudo-op turns off this
warning. .require_canonical_reg_names
turns it back on.
The assembler supports several modifiers when using symbol addresses in TILEPro instruction operands. The general syntax is the following:
modifier(symbol)
The following modifiers are supported:
lo16
hi16
ha16
ha16(N)
is identical to hi16(N)
, except if
lo16(N)
is negative it adds one to the hi16(N)
value. This way lo16
and ha16
can be added to create any
32-bit value using auli
. For example, here is how you move an
arbitrary 32-bit address into r3:
moveli r3, lo16(sym) auli r3, r3, ha16(sym)
got
got_lo16
got_hi16
got_ha16
got_hi16
, but it adds one if
got_lo16
of the input value is negative.
plt
tls_gd
tls_gd_lo16
tls_gd_hi16
tls_gd_ha16
tls_gd_hi16
, but it adds one to the value
if tls_gd_lo16
of the input value is negative.
tls_ie
tls_ie_lo16
tls_ie_hi16
tls_ie_ha16
tls_ie_hi16
, but it adds one to the value
if tls_ie_lo16
of the input value is negative.
tls_le
tls_le_lo16
tls_le_hi16
tls_le_ha16
tls_le_hi16
, but it adds one to the value
if tls_le_lo16
of the input value is negative.
tls_gd_call
tls_gd_add
tls_ie_load
.align
expression [,
expression]
.allow_suspicious_bundles
.no_allow_suspicious_bundles
.require_canonical_reg_names
.no_require_canonical_reg_names
as
supports the following additional command-line options
for the V850 processor family:
-wsigned_overflow
-wunsigned_overflow
-mv850
-mv850e
-mv850e1
-mv850any
-mv850e2
-mv850e2v3
-mv850e2v4
-mv850e3v5
-mrelax
-mgcc-abi
-mrh850-abi
-m8byte-align
-m4byte-align
-msoft-float
e2v3
.
-mhard-float
e2v3
and later architectures.
‘#’ is the line comment character. If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
Two dashes (‘--’) can also be used to start a line comment.
The ‘;’ character can be used to separate statements on the same line.
as
supports the following names for registers:
general register 0
general register 1
general register 2
general register 3
general register 4
general register 5
general register 6
general register 7
general register 8
general register 9
general register 10
general register 11
general register 12
general register 13
general register 14
general register 15
general register 16
general register 17
general register 18
general register 19
general register 20
general register 21
general register 22
general register 23
general register 24
general register 25
general register 26
general register 27
general register 28
general register 29
general register 30
general register 31
system register 0
system register 1
system register 2
system register 3
system register 4
system register 5
system register 16
system register 17
system register 18
system register 19
system register 20
The V850 family uses ieee floating-point numbers.
.offset
<expression>.section "name", <type>
.v850
.v850e
.v850e1
.v850e2
.v850e2v3
.v850e2v4
.v850e3v5
as
implements all the standard V850 opcodes.
as
also implements the following pseudo ops:
hi0()
‘mulhi hi0(here - there), r5, r6’
computes the difference between the address of labels 'here' and 'there', takes the upper 16 bits of this difference, shifts it down 16 bits and then multiplies it by the lower 16 bits in register 5, putting the result into register 6.
lo()
‘addi lo(here - there), r5, r6’
computes the difference between the address of labels 'here' and 'there', takes the lower 16 bits of this difference and adds it to register 5, putting the result into register 6.
hi()
‘movhi hi(here), r0, r6’ ‘movea lo(here), r6, r6’
The reason for this special behaviour is that movea performs a sign extension on its immediate operand. So for example if the address of 'here' was 0xFFFFFFFF then without the special behaviour of the hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the movea instruction would takes its immediate operand, 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With the hi() pseudo op adding in the top bit of the lo() pseudo op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - the right value.
hilo()
‘mov hilo(here), r6’
computes the absolute address of label 'here' and puts the result into register 6.
sdaoff()
‘ld.w sdaoff(_a_variable)[gp],r6’
loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +/- 32K of the address held in the GP register. [Note the linker assumes that the GP register contains a fixed address set to the address of the label called '__gp'. This can either be set up automatically by the linker, or specifically set by using the ‘--defsym __gp=<value>’ command-line option].
tdaoff()
‘sld.w tdaoff(_a_variable)[ep],r6’
loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +256 bytes of the address held in the EP register. [Note the linker assumes that the EP register contains a fixed address set to the address of the label called '__ep'. This can either be set up automatically by the linker, or specifically set by using the ‘--defsym __ep=<value>’ command-line option].
zdaoff()
‘movea zdaoff(_a_variable),zero,r6’
puts the address of the label '_a_variable' into register 6, assuming that the label is somewhere within the first 32K of memory. (Strictly speaking it also possible to access the last 32K of memory as well, as the offsets are signed).
ctoff()
‘callt ctoff(table_func1)’
will put the call the function whose address is held in the call table at the location labeled 'table_func1'.
.longcall name
name
. The linker will attempt to shorten this call
sequence if name
is within a 22bit offset of the call. Only
valid if the -mrelax
command-line switch has been enabled.
.longjump name
name
. The linker will attempt to shorten this code
sequence if name
is within a 22bit offset of the jump. Only
valid if the -mrelax
command-line switch has been enabled.
For information on the V850 instruction set, see V850 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual from NEC. Ltd.
The Vax version of as
accepts any of the following options,
gives a warning message that the option was ignored and proceeds.
These options are for compatibility with scripts designed for other
people's assemblers.
-D (Debug)
-S (Symbol Table)
-T (Token Trace)
-d (Displacement size for JUMPs)
-V (Virtualize Interpass Temporary File)
as
always does this, so this
option is redundant.
-J (JUMPify Longer Branches)
-t (Temporary File Directory)
as
does not use a temporary disk file, this
option makes no difference. ‘-t’ needs exactly one
filename.
The Vax version of the assembler accepts additional options when compiled for VMS:
The ‘-h n’ option determines how we map names. This takes
several values. No ‘-h’ switch at all allows case hacking as
described above. A value of zero (‘-h0’) implies names should be
upper case, and inhibits the case hack. A value of 2 (‘-h2’)
implies names should be all lower case, with no case hack. A value of 3
(‘-h3’) implies that case should be preserved. The value 1 is
unused. The -H
option directs as
to display
every mapped symbol during assembly.
Symbols whose names include a dollar sign ‘$’ are exceptions to the general name mapping. These symbols are normally only used to reference VMS library names. Such symbols are always mapped to upper case.
as
to truncate any symbol
name larger than 31 characters. The ‘-+’ option also prevents some
code following the ‘_main’ symbol normally added to make the object
file compatible with Vax-11 "C".
as
version 1.x.
as
to print every symbol
which was changed by case mapping.
Conversion of flonums to floating point is correct, and compatible with previous assemblers. Rounding is towards zero if the remainder is exactly half the least significant bit.
D
, F
, G
and H
floating point formats
are understood.
Immediate floating literals (e.g. ‘S`$6.9’) are rendered correctly. Again, rounding is towards zero in the boundary case.
The .float
directive produces f
format numbers.
The .double
directive produces d
format numbers.
The Vax version of the assembler supports four directives for generating Vax floating point constants. They are described in the table below.
.dfloat
d
format 64-bit floating point constants.
.ffloat
f
format 32-bit floating point constants.
.gfloat
g
format 64-bit floating point constants.
.hfloat
h
format 128-bit floating point constants.
All DEC mnemonics are supported. Beware that case...
instructions have exactly 3 operands. The dispatch table that
follows the case...
instruction should be made with
.word
statements. This is compatible with all unix
assemblers we know of.
Certain pseudo opcodes are permitted. They are for branch instructions. They expand to the shortest branch instruction that reaches the target. Generally these mnemonics are made by substituting ‘j’ for ‘b’ at the start of a DEC mnemonic. This feature is included both for compatibility and to help compilers. If you do not need this feature, avoid these opcodes. Here are the mnemonics, and the code they can expand into.
jbsb
jbr
jr
j
CONDneq
, nequ
, eql
, eqlu
, gtr
,
geq
, lss
, gtru
, lequ
, vc
, vs
,
gequ
, cc
, lssu
, cs
.
COND may also be one of the bit tests
bs
, bc
, bss
, bcs
, bsc
, bcc
,
bssi
, bcci
, lbs
, lbc
.
NOTCOND is the opposite condition to COND.
jacb
Xb d f g h l w
.
OPCODE ..., foo ; brb bar ; foo: jmp ... ; bar:
jaob
YYYlss leq
.
jsob
ZZZgeq gtr
.
OPCODE ..., foo ; brb bar ; foo: brw destination ; bar:
OPCODE ..., foo ; brb bar ; foo: jmp destination ; bar:
aobleq
aoblss
sobgeq
sobgtr
OPCODE ..., foo ; brb bar ; foo: brw destination ; bar:
OPCODE ..., foo ; brb bar ; foo: jmp destination ; bar:
The immediate character is ‘$’ for Unix compatibility, not ‘#’ as DEC writes it.
The indirect character is ‘*’ for Unix compatibility, not ‘@’ as DEC writes it.
The displacement sizing character is ‘`’ (an accent grave) for
Unix compatibility, not ‘^’ as DEC writes it. The letter
preceding ‘`’ may have either case. ‘G’ is not
understood, but all other letters (b i l s w
) are understood.
Register names understood are r0 r1 r2 ... r15 ap fp sp
pc
. Upper and lower case letters are equivalent.
For instance
tstb *w`$4(r5)
Any expression is permitted in an operand. Operands are comma separated.
Vax bit fields can not be assembled with as
. Someone
can add the required code if they really need it.
The presence of a ‘#’ appearing anywhere on a line indicates the start of a comment that extends to the end of that line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The ‘;’ character can be used to separate statements on the same line.
‘#’ is the line comment character. If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
A semicolon (‘;’) can be used to start a comment that extends from wherever the character appears on the line up to the end of the line.
The ‘|’ character can be used to separate statements on the same line.
.16bit_pointers
.32bit_pointers
.no_pointers
as
implements all the standard XStormy16 opcodes.
as
also implements the following pseudo ops:
@lo()
‘add r6, @lo(here - there)’
computes the difference between the address of labels 'here' and 'there', takes the lower 16 bits of this difference and adds it to register 6.
@hi()
‘addc r7, @hi(here - there)’
computes the difference between the address of labels 'here' and 'there', takes the upper 16 bits of this difference, shifts it down 16 bits and then adds it, along with the carry bit, to the value in register 7.
This chapter covers features of the gnu assembler that are specific to the Xtensa architecture. For details about the Xtensa instruction set, please consult the Xtensa Instruction Set Architecture (ISA) Reference Manual.
--text-section-literals | --no-text-section-literals
L32R
instructions in the text section. Literals are grouped into
pools following .literal_position
directives or preceding
ENTRY
instructions. These options only affect literals referenced
via PC-relative L32R
instructions; literals for absolute mode
L32R
instructions are handled separately.
See literal.
--auto-litpools | --no-auto-litpools
.literal_position
directives are not
required. This may be necessary for very large functions, where single
literal pool at the beginning of the function may not be reachable by
L32R
instructions at the end. These options only affect
literals referenced via PC-relative L32R
instructions; literals
for absolute mode L32R
instructions are handled separately.
When used together with ‘--text-section-literals’,
‘--auto-litpools’ takes precedence.
See literal.
--absolute-literals | --no-absolute-literals
L32R
instructions use absolute
or PC-relative addressing. If the processor includes the absolute
addressing option, the default is to use absolute L32R
relocations. Otherwise, only the PC-relative L32R
relocations
can be used.
--target-align | --no-target-align
LOOP
that
have fixed alignment requirements.
--longcalls | --no-longcalls
--transform | --no-transform
--rename-section
oldname=
newname--trampolines | --no-trampolines
Block comments are delimited by ‘/*’ and ‘*/’. End of line comments may be introduced with either ‘#’ or ‘//’.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma-separated list of operands:
opcode [operand, ...]
Instructions must be separated by a newline or semicolon (‘;’).
FLIX instructions, which bundle multiple opcodes together in a single instruction, are specified by enclosing the bundled opcodes inside braces:
{ [format] opcode0 [operands] opcode1 [operands] opcode2 [operands] ... }
The opcodes in a FLIX instruction are listed in the same order as the corresponding instruction slots in the TIE format declaration. Directives and labels are not allowed inside the braces of a FLIX instruction. A particular TIE format name can optionally be specified immediately after the opening brace, but this is usually unnecessary. The assembler will automatically search for a format that can encode the specified opcodes, so the format name need only be specified in rare cases where there is more than one applicable format and where it matters which of those formats is used. A FLIX instruction can also be specified on a single line by separating the opcodes with semicolons:
{ [format;] opcode0 [operands]; opcode1 [operands]; opcode2 [operands]; ... }
If an opcode can only be encoded in a FLIX instruction but is not specified as part of a FLIX bundle, the assembler will choose the smallest format where the opcode can be encoded and will fill unused instruction slots with no-ops.
See the Xtensa Instruction Set Architecture (ISA) Reference Manual for a complete list of opcodes and descriptions of their semantics.
If an opcode name is prefixed with an underscore character (‘_’), as will not transform that instruction in any way. The underscore prefix disables both optimization (see Xtensa Optimizations) and relaxation (see Xtensa Relaxation) for that particular instruction. Only use the underscore prefix when it is essential to select the exact opcode produced by the assembler. Using this feature unnecessarily makes the code less efficient by disabling assembler optimization and less flexible by disabling relaxation.
Note that this special handling of underscore prefixes only applies to
Xtensa opcodes, not to either built-in macros or user-defined macros.
When an underscore prefix is used with a macro (e.g., _MOV
), it
refers to a different macro. The assembler generally provides built-in
macros both with and without the underscore prefix, where the underscore
versions behave as if the underscore carries through to the instructions
in the macros. For example, _MOV
may expand to _MOV.N
.
The underscore prefix only applies to individual instructions, not to
series of instructions. For example, if a series of instructions have
underscore prefixes, the assembler will not transform the individual
instructions, but it may insert other instructions between them (e.g.,
to align a LOOP
instruction). To prevent the assembler from
modifying a series of instructions as a whole, use the
no-transform
directive. See transform.
The assembly syntax for a register file entry is the “short” name for
a TIE register file followed by the index into that register file. For
example, the general-purpose AR
register file has a short name of
a
, so these registers are named a0
...a15
.
As a special feature, sp
is also supported as a synonym for
a1
. Additional registers may be added by processor configuration
options and by designer-defined TIE extensions. An initial ‘$’
character is optional in all register names.
The optimizations currently supported by as are generation of density instructions where appropriate and automatic branch target alignment.
The Xtensa instruction set has a code density option that provides
16-bit versions of some of the most commonly used opcodes. Use of these
opcodes can significantly reduce code size. When possible, the
assembler automatically translates instructions from the core
Xtensa instruction set into equivalent instructions from the Xtensa code
density option. This translation can be disabled by using underscore
prefixes (see Opcode Names), by using the
‘--no-transform’ command-line option (see Command Line Options), or by using the no-transform
directive
(see transform).
It is a good idea not to use the density instructions directly. The assembler will automatically select dense instructions where possible. If you later need to use an Xtensa processor without the code density option, the same assembly code will then work without modification.
The Xtensa assembler will automatically align certain instructions, both to optimize performance and to satisfy architectural requirements.
As an optimization to improve performance, the assembler attempts to align branch targets so they do not cross instruction fetch boundaries. (Xtensa processors can be configured with either 32-bit or 64-bit instruction fetch widths.) An instruction immediately following a call is treated as a branch target in this context, because it will be the target of a return from the call. This alignment has the potential to reduce branch penalties at some expense in code size. This optimization is enabled by default. You can disable it with the ‘--no-target-align’ command-line option (see Command-line Options).
The target alignment optimization is done without adding instructions that could increase the execution time of the program. If there are density instructions in the code preceding a target, the assembler can change the target alignment by widening some of those instructions to the equivalent 24-bit instructions. Extra bytes of padding can be inserted immediately following unconditional jump and return instructions. This approach is usually successful in aligning many, but not all, branch targets.
The LOOP
family of instructions must be aligned such that the
first instruction in the loop body does not cross an instruction fetch
boundary (e.g., with a 32-bit fetch width, a LOOP
instruction
must be on either a 1 or 2 mod 4 byte boundary). The assembler knows
about this restriction and inserts the minimal number of 2 or 3 byte
no-op instructions to satisfy it. When no-op instructions are added,
any label immediately preceding the original loop will be moved in order
to refer to the loop instruction, not the newly generated no-op
instruction. To preserve binary compatibility across processors with
different fetch widths, the assembler conservatively assumes a 32-bit
fetch width when aligning LOOP
instructions (except if the first
instruction in the loop is a 64-bit instruction).
Previous versions of the assembler automatically aligned ENTRY
instructions to 4-byte boundaries, but that alignment is now the
programmer's responsibility.
When an instruction operand is outside the range allowed for that
particular instruction field, as can transform the code
to use a functionally-equivalent instruction or sequence of
instructions. This process is known as relaxation. This is
typically done for branch instructions because the distance of the
branch targets is not known until assembly-time. The Xtensa assembler
offers branch relaxation and also extends this concept to function
calls, MOVI
instructions and other instructions with immediate
fields.
When the target of a branch is too far away from the branch itself, i.e., when the offset from the branch to the target is too large to fit in the immediate field of the branch instruction, it may be necessary to replace the branch with a branch around a jump. For example,
beqz a2, L
may result in:
bnez.n a2, M j L M:
(The BNEZ.N
instruction would be used in this example only if the
density option is available. Otherwise, BNEZ
would be used.)
This relaxation works well because the unconditional jump instruction has a much larger offset range than the various conditional branches. However, an error will occur if a branch target is beyond the range of a jump instruction. as cannot relax unconditional jumps. Similarly, an error will occur if the original input contains an unconditional jump to a target that is out of range.
Branch relaxation is enabled by default. It can be disabled by using
underscore prefixes (see Opcode Names), the
‘--no-transform’ command-line option (see Command-line Options), or the no-transform
directive
(see transform).
Function calls may require relaxation because the Xtensa immediate call
instructions (CALL0
, CALL4
, CALL8
and
CALL12
) provide a PC-relative offset of only 512 Kbytes in either
direction. For larger programs, it may be necessary to use indirect
calls (CALLX0
, CALLX4
, CALLX8
and CALLX12
)
where the target address is specified in a register. The Xtensa
assembler can automatically relax immediate call instructions into
indirect call instructions. This relaxation is done by loading the
address of the called function into the callee's return address register
and then using a CALLX
instruction. So, for example:
call8 func
might be relaxed to:
.literal .L1, func l32r a8, .L1 callx8 a8
Because the addresses of targets of function calls are not generally known until link-time, the assembler must assume the worst and relax all the calls to functions in other source files, not just those that really will be out of range. The linker can recognize calls that were unnecessarily relaxed, and it will remove the overhead introduced by the assembler for those cases where direct calls are sufficient.
Call relaxation is disabled by default because it can have a negative
effect on both code size and performance, although the linker can
usually eliminate the unnecessary overhead. If a program is too large
and some of the calls are out of range, function call relaxation can be
enabled using the ‘--longcalls’ command-line option or the
longcalls
directive (see longcalls).
Jump instruction may require relaxation because the Xtensa jump instruction
(J
) provide a PC-relative offset of only 128 Kbytes in either
direction. One option is to use jump long (J.L
) instruction, which
depending on jump distance may be assembled as jump (J
) or indirect
jump (JX
). However it needs a free register. When there's no spare
register it is possible to plant intermediate jump sites (trampolines)
between the jump instruction and its target. These sites may be located in
areas unreachable by normal code execution flow, in that case they only
contain intermediate jumps, or they may be inserted in the middle of code
block, in which case there's an additional jump from the beginning of the
trampoline to the instruction past its end. So, for example:
j 1f ... retw ... mov a10, a2 call8 func ... 1: ...
might be relaxed to:
j .L0_TR_1 ... retw .L0_TR_1: j 1f ... mov a10, a2 call8 func ... 1: ...
or to:
j .L0_TR_1 ... retw ... mov a10, a2 j .L0_TR_0 .L0_TR_1: j 1f .L0_TR_0: call8 func ... 1: ...
The Xtensa assembler uses trampolines with jump around only when it cannot find suitable unreachable trampoline. There may be multiple trampolines between the jump instruction and its target.
This relaxation does not apply to jumps to undefined symbols, assuming they will reach their targets once resolved.
Jump relaxation is enabled by default because it does not affect code size or performance while the code itself is small. This relaxation may be disabled completely with ‘--no-trampolines’ or ‘--no-transform’ command-line options (see Command-line Options).
The assembler normally performs the following other relaxations. They
can be disabled by using underscore prefixes (see Opcode Names), the ‘--no-transform’ command-line option
(see Command-line Options), or the
no-transform
directive (see transform).
The MOVI
machine instruction can only materialize values in the
range from -2048 to 2047. Values outside this range are best
materialized with L32R
instructions. Thus:
movi a0, 100000
is assembled into the following machine code:
.literal .L1, 100000 l32r a0, .L1
The L8UI
machine instruction can only be used with immediate
offsets in the range from 0 to 255. The L16SI
and L16UI
machine instructions can only be used with offsets from 0 to 510. The
L32I
machine instruction can only be used with offsets from 0 to
1020. A load offset outside these ranges can be materialized with
an L32R
instruction if the destination register of the load
is different than the source address register. For example:
l32i a1, a0, 2040
is translated to:
.literal .L1, 2040 l32r a1, .L1 add a1, a0, a1 l32i a1, a1, 0
If the load destination and source address register are the same, an out-of-range offset causes an error.
The Xtensa ADDI
instruction only allows immediate operands in the
range from -128 to 127. There are a number of alternate instruction
sequences for the ADDI
operation. First, if the
immediate is 0, the ADDI
will be turned into a MOV.N
instruction (or the equivalent OR
instruction if the code density
option is not available). If the ADDI
immediate is outside of
the range -128 to 127, but inside the range -32896 to 32639, an
ADDMI
instruction or ADDMI
/ADDI
sequence will be
used. Finally, if the immediate is outside of this range and a free
register is available, an L32R
/ADD
sequence will be used
with a literal allocated from the literal pool.
For example:
addi a5, a6, 0 addi a5, a6, 512 addi a5, a6, 513 addi a5, a6, 50000
is assembled into the following:
.literal .L1, 50000 mov.n a5, a6 addmi a5, a6, 0x200 addmi a5, a6, 0x200 addi a5, a5, 1 l32r a5, .L1 add a5, a6, a5
The Xtensa assembler supports a region-based directive syntax:
.begin directive [options] ... .end directive
All the Xtensa-specific directives that apply to a region of code use this syntax.
The directive applies to code between the .begin
and the
.end
. The state of the option after the .end
reverts to
what it was before the .begin
.
A nested .begin
/.end
region can further
change the state of the directive without having to be aware of its
outer state. For example, consider:
.begin no-transform L: add a0, a1, a2 .begin transform M: add a0, a1, a2 .end transform N: add a0, a1, a2 .end no-transform
The ADD
opcodes at L
and N
in the outer
no-transform
region both result in ADD
machine instructions,
but the assembler selects an ADD.N
instruction for the
ADD
at M
in the inner transform
region.
The advantage of this style is that it works well inside macros which can preserve the context of their callers.
The following directives are available:
The schedule
directive is recognized only for compatibility with
Tensilica's assembler.
.begin [no-]schedule .end [no-]schedule
This directive is ignored and has no effect on as.
The longcalls
directive enables or disables function call
relaxation. See Function Call Relaxation.
.begin [no-]longcalls .end [no-]longcalls
Call relaxation is disabled by default unless the ‘--longcalls’
command-line option is specified. The longcalls
directive
overrides the default determined by the command-line options.
This directive enables or disables all assembler transformation, including relaxation (see Xtensa Relaxation) and optimization (see Xtensa Optimizations).
.begin [no-]transform .end [no-]transform
Transformations are enabled by default unless the ‘--no-transform’
option is used. The transform
directive overrides the default
determined by the command-line options. An underscore opcode prefix,
disabling transformation of that opcode, always takes precedence over
both directives and command-line flags.
The .literal
directive is used to define literal pool data, i.e.,
read-only 32-bit data accessed via L32R
instructions.
.literal label, value[, value...]
This directive is similar to the standard .word
directive, except
that the actual location of the literal data is determined by the
assembler and linker, not by the position of the .literal
directive. Using this directive gives the assembler freedom to locate
the literal data in the most appropriate place and possibly to combine
identical literals. For example, the code:
entry sp, 40 .literal .L1, sym l32r a4, .L1
can be used to load a pointer to the symbol sym
into register
a4
. The value of sym
will not be placed between the
ENTRY
and L32R
instructions; instead, the assembler puts
the data in a literal pool.
Literal pools are placed by default in separate literal sections;
however, when using the ‘--text-section-literals’
option (see Command-line Options), the literal
pools for PC-relative mode L32R
instructions
are placed in the current section.3
These text section literal
pools are created automatically before ENTRY
instructions and
manually after ‘.literal_position’ directives (see literal_position). If there are no preceding
ENTRY
instructions, explicit .literal_position
directives
must be used to place the text section literal pools; otherwise,
as will report an error.
When literals are placed in separate sections, the literal section names
are derived from the names of the sections where the literals are
defined. The base literal section names are .literal
for
PC-relative mode L32R
instructions and .lit4
for absolute
mode L32R
instructions (see absolute-literals). These base names are used for literals defined in
the default .text
section. For literals defined in other
sections or within the scope of a literal_prefix
directive
(see literal_prefix), the following rules
determine the literal section name:
.literal
or .lit4
name, with a period to separate the base
name and group name. The literal section is also made a member of the
group.
literal_prefix
value) begins with
“.gnu.linkonce.
kind.
”, the literal section name is formed
by replacing “.
kind” with the base .literal
or
.lit4
name. For example, for literals defined in a section named
.gnu.linkonce.t.func
, the literal section will be
.gnu.linkonce.literal.func
or .gnu.linkonce.lit4.func
.
literal_prefix
value) ends with
.text
, the literal section name is formed by replacing that
suffix with the base .literal
or .lit4
name. For example,
for literals defined in a section named .iram0.text
, the literal
section will be .iram0.literal
or .iram0.lit4
.
.literal
or .lit4
name as a
suffix to the current section name (or literal_prefix
value).
When using ‘--text-section-literals’ to place literals inline
in the section being assembled, the .literal_position
directive
can be used to mark a potential location for a literal pool.
.literal_position
The .literal_position
directive is ignored when the
‘--text-section-literals’ option is not used or when
L32R
instructions use the absolute addressing mode.
The assembler will automatically place text section literal pools
before ENTRY
instructions, so the .literal_position
directive is only needed to specify some other location for a literal
pool. You may need to add an explicit jump instruction to skip over an
inline literal pool.
For example, an interrupt vector does not begin with an ENTRY
instruction so the assembler will be unable to automatically find a good
place to put a literal pool. Moreover, the code for the interrupt
vector must be at a specific starting address, so the literal pool
cannot come before the start of the code. The literal pool for the
vector must be explicitly positioned in the middle of the vector (before
any uses of the literals, due to the negative offsets used by
PC-relative L32R
instructions). The .literal_position
directive can be used to do this. In the following code, the literal
for ‘M’ will automatically be aligned correctly and is placed after
the unconditional jump.
.global M code_start: j continue .literal_position .align 4 continue: movi a4, M
The literal_prefix
directive allows you to override the default
literal section names, which are derived from the names of the sections
where the literals are defined.
.begin literal_prefix [name] .end literal_prefix
For literals defined within the delimited region, the literal section names are derived from the name argument instead of the name of the current section. The rules used to derive the literal section names do not change. See literal. If the name argument is omitted, the literal sections revert to the defaults. This directive has no effect when using the ‘--text-section-literals’ option (see Command-line Options).
The absolute-literals
and no-absolute-literals
directives control the absolute vs. PC-relative mode for L32R
instructions. These are relevant only for Xtensa configurations that
include the absolute addressing option for L32R
instructions.
.begin [no-]absolute-literals .end [no-]absolute-literals
These directives do not change the L32R
mode—they only cause
the assembler to emit the appropriate kind of relocation for L32R
instructions and to place the literal values in the appropriate section.
To change the L32R
mode, the program must write the
LITBASE
special register. It is the programmer's responsibility
to keep track of the mode and indicate to the assembler which mode is
used in each region of code.
If the Xtensa configuration includes the absolute L32R
addressing
option, the default is to assume absolute L32R
addressing unless
the ‘--no-absolute-literals’ command-line option is specified.
Otherwise, the default is to assume PC-relative L32R
addressing.
The absolute-literals
directive can then be used to override
the default determined by the command-line options.
The Zilog Z80 and Ascii R800 version of as
have a few machine
dependent options.
as
uses Z80 instruction names
for the R800 processor, as far as they exist.
The assembler syntax closely follows the 'Z80 family CPU User Manual' by Zilog. In expressions a single ‘=’ may be used as “is equal to” comparison operator.
Suffices can be used to indicate the radix of integer constants; ‘H’ or ‘h’ for hexadecimal, ‘D’ or ‘d’ for decimal, ‘Q’, ‘O’, ‘q’ or ‘o’ for octal, and ‘B’ for binary.
The suffix ‘b’ denotes a backreference to local label.
The semicolon ‘;’ is the line comment character;
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
The Z80 assembler does not support a line separator character.
The dollar sign ‘$’ can be used as a prefix for hexadecimal numbers and as a symbol denoting the current location counter.
A backslash ‘\’ is an ordinary character for the Z80 assembler.
The single quote ‘'’ must be followed by a closing quote. If there is one character in between, it is a character constant, otherwise it is a string constant.
The registers are referred to with the letters assigned to them by Zilog. In addition as recognizes ‘ixl’ and ‘ixh’ as the least and most significant octet in ‘ix’, and similarly ‘iyl’ and ‘iyh’ as parts of ‘iy’.
Upper and lower case are equivalent in register names, opcodes, condition codes and assembler directives. The case of letters is significant in labels and symbol names. The case is also important to distinguish the suffix ‘b’ for a backward reference to a local label from the suffix ‘B’ for a number in binary notation.
Floating-point numbers are not supported.
as for the Z80 supports some additional directives for compatibility with other assemblers.
These are the additional directives in as
for the Z80:
db
expression|
string[,
expression|
string...]
defb
expression|
string[,
expression|
string...]
dw
expression[,
expression...]
defw
expression[,
expression...]
d24
expression[,
expression...]
def24
expression[,
expression...]
d32
expression[,
expression...]
def32
expression[,
expression...]
ds
count[,
value]
defs
count[,
value]
equ
expression defl
expressionequ
is used, it is an error if symbol is already defined.
Symbols defined with equ
are not protected from redefinition.
set
psect
nameIn line with common practice, Z80 mnemonics are used for both the Z80 and the R800.
In many instructions it is possible to use one of the half index
registers (‘ixl’,‘ixh’,‘iyl’,‘iyh’) in stead of an
8-bit general purpose register. This yields instructions that are
documented on the R800 and undocumented on the Z80.
Similarly in f,(c)
is documented on the R800 and undocumented on
the Z80.
The assembler also supports the following undocumented Z80-instructions, that have not been adopted in the R800 instruction set:
out (c),0
sli
m = (
m<<1)+1
, the operand m can
be any operand that is valid for ‘sla’. One can use ‘sll’ as a
synonym for ‘sli’.
(ix+
d),
rld r, (ix+d) opc r ld (ix+d), r
The operation ‘opc’ may be any of ‘res b,’,
‘set b,’, ‘rl’, ‘rlc’, ‘rr’, ‘rrc’,
‘sla’, ‘sli’, ‘sra’ and ‘srl’, and the register
‘r’ may be any of ‘a’, ‘b’, ‘c’, ‘d’,
‘e’, ‘h’ and ‘l’.
(iy+
d),
rThe web site at http://www.z80.info is a good starting place to find more information on programming the Z80.
The Z8000 as supports both members of the Z8000 family: the unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit addresses.
When the assembler is in unsegmented mode (specified with the
unsegm
directive), an address takes up one word (16 bit)
sized register. When the assembler is in segmented mode (specified with
the segm
directive), a 24-bit address takes up a long (32 bit)
register. See Assembler Directives for the Z8000,
for a list of other Z8000 specific assembler directives.
‘!’ is the line comment character.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).
You can use ‘;’ instead of a newline to separate statements.
The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer to different sized groups of registers by register number, with the prefix ‘r’ for 16 bit registers, ‘rr’ for 32 bit registers and ‘rq’ for 64 bit registers. You can also refer to the contents of the first eight (of the sixteen 16 bit registers) by bytes. They are named ‘rln’ and ‘rhn’.
byte registers
rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
word registers
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
long word registers
rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
quad word registers
rq0 rq4 rq8 rq12
as understands the following addressing modes for the Z8000:
rl
nrh
nr
nrr
nrq
n@r
n@rr
naddress(r
n)
r
n(#
imm)
rr
n(#
imm)
r
n(r
m)
rr
n(r
m)
#
xxThe Z8000 port of as includes additional assembler directives, for compatibility with other Z8000 assemblers. These do not begin with ‘.’ (unlike the ordinary as directives).
segm
.z8001
unsegm
.z8002
name
.file
global
.global
wval
.word
lval
.long
bval
.byte
sval
sval
expects one string literal, delimited by
single quotes. It assembles each byte of the string into consecutive
addresses. You can use the escape sequence ‘%xx’ (where
xx represents a two-digit hexadecimal number) to represent the
character whose ascii value is xx. Use this feature to
describe single quote and other characters that may not appear in string
literals as themselves. For example, the C statement ‘char *a = "he said \"it's 50% off\"";’ is represented in Z8000 assembly language
(shown with the assembler output in hex at the left) as
68652073 sval 'he said %22it%27s 50%25 off%22%00' 61696420 22697427 73203530 25206F66 662200
rsect
.section
block
.space
even
.align
; aligns output to even byte boundary.
For detailed information on the Z8000 machine instruction set, see Z8000 Technical Manual.
Your bug reports play an essential role in making as reliable.
Reporting a bug may help you by bringing a solution to your problem, or it may not. But in any case the principal function of a bug report is to help the entire community by making the next version of as work better. Bug reports are your contribution to the maintenance of as.
In order for a bug report to serve its purpose, you must include the information that enables us to fix the bug.
If you are not sure whether you have found a bug, here are some guidelines:
A number of companies and individuals offer support for gnu products. If you obtained as from a support organization, we recommend you contact that organization first.
You can find contact information for many support companies and individuals in the file etc/SERVICE in the gnu Emacs distribution.
In any event, we also recommend that you send bug reports for as to http://www.sourceware.org/bugzilla/.
The fundamental principle of reporting bugs usefully is this: report all the facts. If you are not sure whether to state a fact or leave it out, state it!
Often people omit facts because they think they know what causes the problem and assume that some details do not matter. Thus, you might assume that the name of a symbol you use in an example does not matter. Well, probably it does not, but one cannot be sure. Perhaps the bug is a stray memory reference which happens to fetch from the location where that name is stored in memory; perhaps, if the name were different, the contents of that location would fool the assembler into doing the right thing despite the bug. Play it safe and give a specific, complete example. That is the easiest thing for you to do, and the most helpful.
Keep in mind that the purpose of a bug report is to enable us to fix the bug if it is new to us. Therefore, always write your bug reports on the assumption that the bug has not been reported previously.
Sometimes people give a few sketchy facts and ask, “Does this ring a bell?” This cannot help us fix a bug, so it is basically useless. We respond by asking for enough details to enable us to investigate. You might as well expedite matters by sending them to begin with.
To enable us to fix the bug, you should include all these things:
Without this, we will not know whether there is any point in looking for the bug in the current version of as.
gcc-2.7
”.
If we were to try to guess the arguments, we would probably guess wrong and then we might not encounter the bug.
gcc
, use
the options ‘-v --save-temps’; this will save the assembler source in a
file with an extension of .s, and also show you exactly how
as is being run.
Of course, if the bug is that as gets a fatal signal, then we will certainly notice it. But if the bug is incorrect output, we might not notice unless it is glaringly wrong. You might as well not give us a chance to make a mistake.
Even if the problem you experience is a fatal signal, you should still say so explicitly. Suppose something strange is going on, such as, your copy of as is out of sync, or you have encountered a bug in the C library on your system. (This has happened!) Your copy might crash and ours would not. If you told us to expect a crash, then when ours fails to crash, we would know that the bug was not happening for us. If you had not told us to expect a crash, then we would not be able to draw any conclusion from our observations.
diff
with the ‘-u’, ‘-c’, or ‘-p’
option. Always send diffs from the old file to the new file. If you even
discuss something in the as source, refer to it by context, not
by line number.
The line numbers in our development sources will not match those in your sources. Your line numbers would convey no useful information to us.
Here are some things that are not necessary:
Often people who encounter a bug spend a lot of time investigating which changes to the input file will make the bug go away and which changes will not affect it.
This is often time consuming and not very useful, because the way we will find the bug is by running a single example under the debugger with breakpoints, not by pure deduction from a series of examples. We recommend that you save your time for something else.
Of course, if you can find a simpler example to report instead of the original one, that is a convenience for us. Errors in the output will be easier to spot, running under the debugger will take less time, and so on.
However, simplification is not vital; if you do not want to do this, report the bug anyway and send us the entire test case you used.
A patch for the bug does help us if it is a good one. But do not omit the necessary information, such as the test case, on the assumption that a patch is all we need. We might see problems with your patch and decide to fix the problem another way, or we might not understand it at all.
Sometimes with a program as complicated as as it is very hard to construct an example that will make the program follow a certain path through the code. If you do not send us the example, we will not be able to construct one, so we will not be able to verify that the bug is fixed.
And if we cannot understand what bug you are trying to fix, or why your patch should be an improvement, we will not install it. A test case will help us to understand.
Such guesses are usually wrong. Even we cannot guess right about such things without first using the debugger to find the facts.
If you have contributed to GAS and your name isn't listed here,
it is not meant as a slight. We just don't know about it. Send mail to the
maintainer, and we'll correct the situation. Currently
the maintainer is Nick Clifton (email address nickc@redhat.com
).
Dean Elsner wrote the original gnu assembler for the VAX.4
Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug information and the 68k series machines, most of the preprocessing pass, and extensive changes in messages.c, input-file.c, write.c.
K. Richard Pixley maintained GAS for a while, adding various enhancements and many bug fixes, including merging support for several processors, breaking GAS up to handle multiple object file format back ends (including heavy rewrite, testing, an integration of the coff and b.out back ends), adding configuration including heavy testing and verification of cross assemblers and file splits and renaming, converted GAS to strictly ANSI C including full prototypes, added support for m680[34]0 and cpu32, did considerable work on i960 including a COFF port (including considerable amounts of reverse engineering), a SPARC opcode file rewrite, DECstation, rs6000, and hp300hpux host ports, updated “know” assertions and made them work, much other reorganization, cleanup, and lint.
Ken Raeburn wrote the high-level BFD interface code to replace most of the code in format-specific I/O modules.
The original VMS support was contributed by David L. Kashtan. Eric Youngdale has done much work with it since.
The Intel 80386 machine description was written by Eliot Dresselhaus.
Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
The Motorola 88k machine description was contributed by Devon Bowen of Buffalo University and Torbjorn Granlund of the Swedish Institute of Computer Science.
Keith Knowles at the Open Software Foundation wrote the original MIPS back end (tc-mips.c, tc-mips.h), and contributed Rose format support (which hasn't been merged in yet). Ralph Campbell worked with the MIPS code to support a.out format.
Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, tc-h8300), and IEEE 695 object file format (obj-ieee), was written by Steve Chamberlain of Cygnus Support. Steve also modified the COFF back end to use BFD for some low-level operations, for use with the H8/300 and AMD 29k targets.
John Gilmore built the AMD 29000 support, added .include
support, and
simplified the configuration of which versions accept which directives. He
updated the 68k machine description so that Motorola's opcodes always produced
fixed-size instructions (e.g., jsr
), while synthetic instructions
remained shrinkable (jbsr
). John fixed many bugs, including true tested
cross-compilation support, and one bug in relaxation that took a week and
required the proverbial one-bit fix.
Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the 68k, completed support for some COFF targets (68k, i386 SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the initial RS/6000 and PowerPC assembler, and made a few other minor patches.
Steve Chamberlain made GAS able to generate listings.
Hewlett-Packard contributed support for the HP9000/300.
Jeff Law wrote GAS and BFD support for the native HPPA object format (SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF object formats). This work was supported by both the Center for Software Science at the University of Utah and Cygnus Support.
Support for ELF format files has been worked on by Mark Eichin of Cygnus Support (original, incomplete implementation for SPARC), Pete Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn of Cygnus Support (sparc, and some initial 64-bit support).
Linas Vepstas added GAS support for the ESA/390 “IBM 370” architecture.
Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD support for openVMS/Alpha.
Timothy Wall, Michael Hayes, and Greg Smart contributed to the various tic* flavors.
David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from Tensilica, Inc. added support for Xtensa processors.
Several engineers at Cygnus Support have also provided many small bug fixes and configuration enhancements.
Jon Beniston added support for the Lattice Mico32 architecture.
Many others have contributed large or small bugfixes and enhancements. If you have contributed significant work and are not mentioned on this list, and want to be, let us know. Some of the history has been lost; we are not intentionally leaving anyone out.
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\"
(doublequote character): Strings \\
(‘\’ character): Strings \b
(backspace character): Strings \
ddd (octal character code): Strings \f
(formfeed character): Strings \n
(newline character): Strings \r
(carriage return character): Strings \t
(tab): Strings \
xd... (hex character code): Strings#
: Comments#APP
: Preprocessing#NO_APP
: Preprocessing$
in symbol names: SH-Chars$
in symbol names: D30V-Chars$
in symbol names: D10V-Chars$a
: ARM Mapping Symbols$acos
math builtin, TIC54X: TIC54X-Builtins$asin
math builtin, TIC54X: TIC54X-Builtins$atan
math builtin, TIC54X: TIC54X-Builtins$atan2
math builtin, TIC54X: TIC54X-Builtins$ceil
math builtin, TIC54X: TIC54X-Builtins$cos
math builtin, TIC54X: TIC54X-Builtins$cosh
math builtin, TIC54X: TIC54X-Builtins$cvf
math builtin, TIC54X: TIC54X-Builtins$cvi
math builtin, TIC54X: TIC54X-Builtins$d
: ARM Mapping Symbols$exp
math builtin, TIC54X: TIC54X-Builtins$fabs
math builtin, TIC54X: TIC54X-Builtins$firstch
subsym builtin, TIC54X: TIC54X-Macros$floor
math builtin, TIC54X: TIC54X-Builtins$fmod
math builtin, TIC54X: TIC54X-Builtins$int
math builtin, TIC54X: TIC54X-Builtins$iscons
subsym builtin, TIC54X: TIC54X-Macros$isdefed
subsym builtin, TIC54X: TIC54X-Macros$ismember
subsym builtin, TIC54X: TIC54X-Macros$isname
subsym builtin, TIC54X: TIC54X-Macros$isreg
subsym builtin, TIC54X: TIC54X-Macros$lastch
subsym builtin, TIC54X: TIC54X-Macros$ldexp
math builtin, TIC54X: TIC54X-Builtins$log
math builtin, TIC54X: TIC54X-Builtins$log10
math builtin, TIC54X: TIC54X-Builtins$max
math builtin, TIC54X: TIC54X-Builtins$min
math builtin, TIC54X: TIC54X-Builtins$pow
math builtin, TIC54X: TIC54X-Builtins$round
math builtin, TIC54X: TIC54X-Builtins$sgn
math builtin, TIC54X: TIC54X-Builtins$sin
math builtin, TIC54X: TIC54X-Builtins$sinh
math builtin, TIC54X: TIC54X-Builtins$sqrt
math builtin, TIC54X: TIC54X-Builtins$structacc
subsym builtin, TIC54X: TIC54X-Macros$structsz
subsym builtin, TIC54X: TIC54X-Macros$symcmp
subsym builtin, TIC54X: TIC54X-Macros$symlen
subsym builtin, TIC54X: TIC54X-Macros$t
: ARM Mapping Symbols$tan
math builtin, TIC54X: TIC54X-Builtins$tanh
math builtin, TIC54X: TIC54X-Builtins$trunc
math builtin, TIC54X: TIC54X-Builtins--
: Command Line--absolute-literals
: Xtensa Options--allow-reg-prefix
: SH Options--alternate
: alternate--auto-litpools
: Xtensa Options--big
: SH Options--dsp
: SH Options--enforce-aligned-data
: Sparc-Aligned-Data--fatal-warnings
: W--fdpic
: SH Options--fix-v4bx
command-line option, ARM: ARM Options--listing-cont-lines
: listing--listing-lhs-width
: listing--listing-lhs-width2
: listing--listing-rhs-width
: listing--little
: SH Options--longcalls
: Xtensa Options--MD
: MD--no-absolute-literals
: Xtensa Options--no-auto-litpools
: Xtensa Options--no-longcalls
: Xtensa Options--no-pad-sections
: no-pad-sections--no-target-align
: Xtensa Options--no-text-section-literals
: Xtensa Options--no-trampolines
: Xtensa Options--no-transform
: Xtensa Options--no-warn
: W--relax
: SH Options--rename-section
: Xtensa Options--renesas
: SH Options--sectname-subst
: Section--small
: SH Options--statistics
: statistics--target-align
: Xtensa Options--text-section-literals
: Xtensa Options--traditional-format
: traditional-format--trampolines
: Xtensa Options--transform
: Xtensa Options--warn
: W-32addr
command-line option, Alpha: Alpha Options-a
: a-ac
: a-ad
: a-ag
: a-ah
: a-al
: a-Aleon
: Sparc-Opts-an
: a-as
: a-Asparc
: Sparc-Opts-Asparcfmaf
: Sparc-Opts-Asparcima
: Sparc-Opts-Asparclet
: Sparc-Opts-Asparclite
: Sparc-Opts-Asparcvis
: Sparc-Opts-Asparcvis2
: Sparc-Opts-Asparcvis3
: Sparc-Opts-Asparcvis3r
: Sparc-Opts-Av6
: Sparc-Opts-Av7
: Sparc-Opts-Av8
: Sparc-Opts-Av9
: Sparc-Opts-Av9a
: Sparc-Opts-Av9b
: Sparc-Opts-Av9c
: Sparc-Opts-Av9d
: Sparc-Opts-Av9e
: Sparc-Opts-Av9m
: Sparc-Opts-Av9v
: Sparc-Opts-big
option, M32R: M32R-Opts-D
: D-D
, ignored on VAX: VAX-Opts-d
, VAX option: VAX-Opts-eabi=
command-line option, ARM: ARM Options-EB
command-line option, ARC: ARC Options-EB
command-line option, ARM: ARM Options-EB
option (MIPS): MIPS Options-EB
option, M32R: M32R-Opts-EL
command-line option, ARC: ARC Options-EL
command-line option, ARM: ARM Options-EL
option (MIPS): MIPS Options-EL
option, M32R: M32R-Opts-f
: f-F
command-line option, Alpha: Alpha Options-G
command-line option, Alpha: Alpha Options-g
command-line option, Alpha: Alpha Options-G
option (MIPS): MIPS Options-I
path: I-J
, ignored on VAX: VAX-Opts-K
: K-k
command-line option, ARM: ARM Options-KPIC
option, M32R: M32R-Opts-L
: L-little
option, M32R: M32R-Opts-M
: M-m4byte-align
command-line option, V850: V850 Options-m8byte-align
command-line option, V850: V850 Options-mall-enabled
command-line option, LM32: LM32 Options-mall-opcodes
command-line option, AVR: AVR Options-mapcs-26
command-line option, ARM: ARM Options-mapcs-32
command-line option, ARM: ARM Options-mapcs-float
command-line option, ARM: ARM Options-mapcs-reentrant
command-line option, ARM: ARM Options-march=
command-line option, ARM: ARM Options-march=
command-line option, TIC6X: TIC6X Options-matpcs
command-line option, ARM: ARM Options-mbarrel-shift-enabled
command-line option, LM32: LM32 Options-mbreak-enabled
command-line option, LM32: LM32 Options-mccs
command-line option, ARM: ARM Options-mcode-density
command-line option, ARC: ARC Options-mconstant-gp
command-line option, IA-64: IA-64 Options-m
cpu command-line option, Alpha: Alpha Options-mcpu=
command-line option, ARM: ARM Options-mcpu=
command-line option, Blackfin: Blackfin Options-mcpu=
cpu command-line option, ARC: ARC Options-mdcache-enabled
command-line option, LM32: LM32 Options-mdebug
command-line option, Alpha: Alpha Options-mdivide-enabled
command-line option, LM32: LM32 Options-mdpfp
command-line option, ARC: ARC Options-mdsbt
command-line option, TIC6X: TIC6X Options-mepiphany
command-line option, Epiphany: Epiphany Options-mepiphany16
command-line option, Epiphany: Epiphany Options-mfdpic
command-line option, Blackfin: Blackfin Options-mfloat-abi=
command-line option, ARM: ARM Options-mfp16-format=
command-line option: ARM Options-mfpu=
command-line option, ARM: ARM Options-mfpuda
command-line option, ARC: ARC Options-mgcc-abi
command-line option, V850: V850 Options-mgcc-isr
command-line option, AVR: AVR Options-mhard-float
command-line option, V850: V850 Options-micache-enabled
command-line option, LM32: LM32 Options-mimplicit-it
command-line option, ARM: ARM Options-mlink-relax
command-line option, AVR: AVR Options-mmcu=
command-line option, AVR: AVR Options-mmultiply-enabled
command-line option, LM32: LM32 Options-mno-dsbt
command-line option, TIC6X: TIC6X Options-mno-fdpic
command-line option, Blackfin: Blackfin Options-mno-link-relax
command-line option, AVR: AVR Options-mno-pic
command-line option, TIC6X: TIC6X Options-mno-skip-bug
command-line option, AVR: AVR Options-mno-wrap
command-line option, AVR: AVR Options-mnopic
command-line option, Blackfin: Blackfin Options-mnps400
command-line option, ARC: ARC Options-mpic
command-line option, TIC6X: TIC6X Options-mpid=
command-line option, TIC6X: TIC6X Options-mrelax
command-line option, ARC: ARC Options-mrelax
command-line option, V850: V850 Options-mrh850-abi
command-line option, V850: V850 Options-mrmw
command-line option, AVR: AVR Options-msign-extend-enabled
command-line option, LM32: LM32 Options-msoft-float
command-line option, V850: V850 Options-mspfp
command-line option, ARC: ARC Options-mthumb
command-line option, ARM: ARM Options-mthumb-interwork
command-line option, ARM: ARM Options-muser-enabled
command-line option, LM32: LM32 Options-mv850
command-line option, V850: V850 Options-mv850any
command-line option, V850: V850 Options-mv850e
command-line option, V850: V850 Options-mv850e1
command-line option, V850: V850 Options-mv850e2
command-line option, V850: V850 Options-mv850e2v3
command-line option, V850: V850 Options-mv850e2v4
command-line option, V850: V850 Options-mv850e3v5
command-line option, V850: V850 Options-mwarn-deprecated
command-line option, ARM: ARM Options-mwarn-syms
command-line option, ARM: ARM Options-no-mdebug
command-line option, Alpha: Alpha Options-no-parallel
option, M32RX: M32R-Opts-nocpp
ignored (MIPS): MIPS Options-noreplace
command-line option, Alpha: Alpha Options-o
: o-O
option, M32RX: M32R-Opts-parallel
option, M32RX: M32R-Opts-R
: R-r800
command-line option, Z80: Z80 Options-relax
command-line option, Alpha: Alpha Options-replace
command-line option, Alpha: Alpha Options-S
, ignored on VAX: VAX-Opts-t
, ignored on VAX: VAX-Opts-T
, ignored on VAX: VAX-Opts-v
: v-V
, redundant on VAX: VAX-Opts-version
: v-W
: W-wsigned_overflow
command-line option, V850: V850 Options-wunsigned_overflow
command-line option, V850: V850 Options-z80
command-line option, Z80: Z80 Options-z8001
command-line option, Z8000: Z8000 Options-z8002
command-line option, Z8000: Z8000 Options.
(symbol): Dot.align
directive, ARM: ARM Directives.align
directive, TILE-Gx: TILE-Gx Directives.align
directive, TILEPro: TILEPro Directives.allow_suspicious_bundles
directive, TILE-Gx: TILE-Gx Directives.allow_suspicious_bundles
directive, TILEPro: TILEPro Directives.arc_attribute
directive, ARC: ARC Directives.arch
directive, ARM: ARM Directives.arch
directive, TIC6X: TIC6X Directives.arch_extension
directive, ARM: ARM Directives.arm
directive, ARM: ARM Directives.big
directive, M32RX: M32R-Directives.bss
directive, ARM: ARM Directives.c6xabi_attribute
directive, TIC6X: TIC6X Directives.cantunwind
directive, ARM: ARM Directives.cantunwind
directive, TIC6X: TIC6X Directives.code
directive, ARM: ARM Directives.cpu
directive, ARM: ARM Directives.dn
and .qn
directives, ARM: ARM Directives.eabi_attribute
directive, ARM: ARM Directives.ehtype
directive, TIC6X: TIC6X Directives.endp
directive, TIC6X: TIC6X Directives.even
directive, ARM: ARM Directives.extend
directive, ARM: ARM Directives.float16
directive, ARM: ARM Directives.float16_format
directive, ARM: ARM Directives.fnend
directive, ARM: ARM Directives.fnstart
directive, ARM: ARM Directives.force_thumb
directive, ARM: ARM Directives.fpu
directive, ARM: ARM Directives.global
: MIPS insn.gnu_attribute 4,
n directive, MIPS: MIPS FP ABI History.gnu_attribute Tag_GNU_MIPS_ABI_FP,
n directive, MIPS: MIPS FP ABI History.handlerdata
directive, ARM: ARM Directives.handlerdata
directive, TIC6X: TIC6X Directives.insn
: MIPS insn.insn
directive, s390: s390 Directives.inst
directive, ARM: ARM Directives.ldouble
directive, ARM: ARM Directives.little
directive, M32RX: M32R-Directives.long
directive, s390: s390 Directives.ltorg
directive, ARM: ARM Directives.ltorg
directive, s390: s390 Directives.m32r
directive, M32R: M32R-Directives.m32r2
directive, M32R2: M32R-Directives.m32rx
directive, M32RX: M32R-Directives.machine
directive, s390: s390 Directives.machinemode
directive, s390: s390 Directives.module
: MIPS assembly options.module fp=
nn directive, MIPS: MIPS FP ABI Selection.movsp
directive, ARM: ARM Directives.nan
directive, MIPS: MIPS NaN Encodings.no_pointers
directive, XStormy16: XStormy16 Directives.nocmp
directive, TIC6X: TIC6X Directives.o
: Object.object_arch
directive, ARM: ARM Directives.packed
directive, ARM: ARM Directives.pad
directive, ARM: ARM Directives.param
on HPPA: HPPA Directives.personality
directive, ARM: ARM Directives.personality
directive, TIC6X: TIC6X Directives.personalityindex
directive, ARM: ARM Directives.personalityindex
directive, TIC6X: TIC6X Directives.pool
directive, ARM: ARM Directives.quad
directive, s390: s390 Directives.req
directive, ARM: ARM Directives.require_canonical_reg_names
directive, TILE-Gx: TILE-Gx Directives.require_canonical_reg_names
directive, TILEPro: TILEPro Directives.save
directive, ARM: ARM Directives.scomm
directive, TIC6X: TIC6X Directives.secrel32
directive, ARM: ARM Directives.set arch=
cpu: MIPS ISA.set at
: MIPS Macros.set at=
reg: MIPS Macros.set autoextend
: MIPS autoextend.set crc
: MIPS ASE Instruction Generation Overrides.set doublefloat
: MIPS Floating-Point.set dsp
: MIPS ASE Instruction Generation Overrides.set dspr2
: MIPS ASE Instruction Generation Overrides.set dspr3
: MIPS ASE Instruction Generation Overrides.set ginv
: MIPS ASE Instruction Generation Overrides.set hardfloat
: MIPS Floating-Point.set insn32
: MIPS assembly options.set loongson-cam
: MIPS ASE Instruction Generation Overrides.set loongson-ext
: MIPS ASE Instruction Generation Overrides.set loongson-ext2
: MIPS ASE Instruction Generation Overrides.set loongson-mmi
: MIPS ASE Instruction Generation Overrides.set macro
: MIPS Macros.set mcu
: MIPS ASE Instruction Generation Overrides.set mdmx
: MIPS ASE Instruction Generation Overrides.set mips16e2
: MIPS ASE Instruction Generation Overrides.set mips3d
: MIPS ASE Instruction Generation Overrides.set mips
n: MIPS ISA.set msa
: MIPS ASE Instruction Generation Overrides.set mt
: MIPS ASE Instruction Generation Overrides.set noat
: MIPS Macros.set noautoextend
: MIPS autoextend.set nocrc
: MIPS ASE Instruction Generation Overrides.set nodsp
: MIPS ASE Instruction Generation Overrides.set nodspr2
: MIPS ASE Instruction Generation Overrides.set nodspr3
: MIPS ASE Instruction Generation Overrides.set noginv
: MIPS ASE Instruction Generation Overrides.set noinsn32
: MIPS assembly options.set noloongson-cam
: MIPS ASE Instruction Generation Overrides.set noloongson-ext
: MIPS ASE Instruction Generation Overrides.set noloongson-ext2
: MIPS ASE Instruction Generation Overrides.set noloongson-mmi
: MIPS ASE Instruction Generation Overrides.set nomacro
: MIPS Macros.set nomcu
: MIPS ASE Instruction Generation Overrides.set nomdmx
: MIPS ASE Instruction Generation Overrides.set nomips16e2
: MIPS ASE Instruction Generation Overrides.set nomips3d
: MIPS ASE Instruction Generation Overrides.set nomsa
: MIPS ASE Instruction Generation Overrides.set nomt
: MIPS ASE Instruction Generation Overrides.set nosmartmips
: MIPS ASE Instruction Generation Overrides.set nosym32
: MIPS Symbol Sizes.set novirt
: MIPS ASE Instruction Generation Overrides.set noxpa
: MIPS ASE Instruction Generation Overrides.set pop
: MIPS Option Stack.set push
: MIPS Option Stack.set singlefloat
: MIPS Floating-Point.set smartmips
: MIPS ASE Instruction Generation Overrides.set softfloat
: MIPS Floating-Point.set sym32
: MIPS Symbol Sizes.set virt
: MIPS ASE Instruction Generation Overrides.set xpa
: MIPS ASE Instruction Generation Overrides.setfp
directive, ARM: ARM Directives.short
directive, s390: s390 Directives.syntax
directive, ARM: ARM Directives.thumb
directive, ARM: ARM Directives.thumb_func
directive, ARM: ARM Directives.thumb_set
directive, ARM: ARM Directives.tlsdescseq
directive, ARM: ARM Directives.unreq
directive, ARM: ARM Directives.unwind_raw
directive, ARM: ARM Directives.v850
directive, V850: V850 Directives.v850e
directive, V850: V850 Directives.v850e1
directive, V850: V850 Directives.v850e2
directive, V850: V850 Directives.v850e2v3
directive, V850: V850 Directives.v850e2v4
directive, V850: V850 Directives.v850e3v5
directive, V850: V850 Directives.vsave
directive, ARM: ARM Directives.z8001
: Z8000 Directives.z8002
: Z8000 Directives16bit_pointers
directive, XStormy16: XStormy16 Directives2byte
directive: 2byte32bit_pointers
directive, XStormy16: XStormy16 Directives4byte
directive: 4byte8byte
directive: 8byte:
(label): Statements@hi
pseudo-op, XStormy16: XStormy16 Opcodes@lo
pseudo-op, XStormy16: XStormy16 Opcodesa.out
: Objecta.out
symbol attributes: a.out SymbolsABORT
directive: ABORT (COFF)abort
directive: Abortabsolute-literals
directive: Absolute Literals DirectiveADDI
instructions, relaxation: Xtensa Immediate RelaxationADR reg,<label>
pseudo op, ARM: ARM OpcodesADRL reg,<label>
pseudo op, ARM: ARM Opcodesalign
directive: Alignalign
directive, SPARC: Sparc-Directivesalign
directive, TIC54X: TIC54X-DirectivesLOOP
instructions: Xtensa Automatic Alignmentarch
directive, M680x0: M68K-Directivesarch
directive, MSP 430: MSP430 Directivesascii
directive: Asciiasciz
directive: Ascizasg
directive, TIC54X: TIC54X-Directivesat
register, MIPS: MIPS Macros\\
): Strings\b
): Stringsbalign
directive: Balignbalignl
directive: Balignbalignw
directive: Balignbes
directive, TIC54X: TIC54X-Directivesblock
: Z8000 Directivesbreak
directive, TIC54X: TIC54X-Directivesbss
directive, TIC54X: TIC54X-Directivesbundle_align_mode
directive: Bundle directivesbundle_lock
directive: Bundle directivesbundle_unlock
directive: Bundle directivesbval
: Z8000 Directivesbyte
directive: Bytebyte
directive, TIC54X: TIC54X-Directivesc_mode
directive, TIC54X: TIC54X-Directivesbackslash-r
): Stringscfi_endproc
directive: CFI directivescfi_fde_data
directive: CFI directivescfi_personality
directive: CFI directivescfi_personality_id
directive: CFI directivescfi_sections
directive: CFI directivescfi_startproc
directive: CFI directiveschar
directive, TIC54X: TIC54X-Directivesclink
directive, TIC54X: TIC54X-Directivescode16
directive, i386: i386-16bitcode16gcc
directive, i386: i386-16bitcode32
directive, i386: i386-16bitcode64
directive, i386: i386-16bitcode64
directive, x86-64: i386-16bitcomm
directive: Commcommon
directive, SPARC: Sparc-Directivescopy
directive, TIC54X: TIC54X-Directivescpu
directive, ARC: ARC Directivescpu
directive, M680x0: M68K-Directivescpu
directive, MSP 430: MSP430 Directivesctbp
register, V850: V850-Regsctoff
pseudo-op, V850: V850 Opcodesctpc
register, V850: V850-Regsctpsw
register, V850: V850-Regsdata
directive: Datadata
directive, TIC54X: TIC54X-Directivesdata1
directive, M680x0: M68K-Directivesdata2
directive, M680x0: M68K-Directivesdbpc
register, V850: V850-Regsdbpsw
register, V850: V850-Regsdc
directive: Dcdcb
directive: Dcbdef
directive: Defdef
directive, TIC54X: TIC54X-Directivesdesc
directive: Desca.out
symbol: Symbol Descdfloat
directive, VAX: VAX-directivesdim
directive: Dimdouble
directive: Doubledouble
directive, i386: i386-Floatdouble
directive, M680x0: M68K-Floatdouble
directive, M68HC11: M68HC11-Floatdouble
directive, RX: RX-Floatdouble
directive, TIC54X: TIC54X-Directivesdouble
directive, VAX: VAX-floatdouble
directive, x86-64: i386-Float\"
): Stringsdrlist
directive, TIC54X: TIC54X-Directivesdrnolist
directive, TIC54X: TIC54X-Directivesds
directive: Dsecr
register, V850: V850-Regseipc
register, V850: V850-Regseipsw
register, V850: V850-Regseject
directive: Ejectelse
directive: Elseelseif
directive: Elseifemsg
directive, TIC54X: TIC54X-Directivesend
directive: Endendef
directive: Endefendfunc
directive: Endfuncendif
directive: Endifendloop
directive, TIC54X: TIC54X-Directivesendm
directive: Macroendm
directive, TIC54X: TIC54X-Directivesendstruct
directive, TIC54X: TIC54X-Directivesendunion
directive, TIC54X: TIC54X-Directivesep
register, V850: V850-Regsequ
directive: Equequ
directive, TIC54X: TIC54X-Directivesequiv
directive: Equiveqv
directive: Eqverr
directive: Erreval
directive, TIC54X: TIC54X-Directiveseven
: Z8000 Directiveseven
directive, M680x0: M68K-Directiveseven
directive, TIC54X: TIC54X-Directivesexitm
directive: MacroextAuxRegister
directive, ARC: ARC DirectivesextCondCode
directive, ARC: ARC DirectivesextCoreRegister
directive, ARC: ARC Directivesextend
directive M680x0: M68K-Floatextend
directive M68HC11: M68HC11-Floatextern
directive: ExternextInstruction
directive, ARC: ARC Directivesfail
directive: Failfar_mode
directive, TIC54X: TIC54X-Directivesfclist
directive, TIC54X: TIC54X-Directivesfcnolist
directive, TIC54X: TIC54X-Directivesfepc
register, V850: V850-Regsfepsw
register, V850: V850-Regsffloat
directive, VAX: VAX-directivesfield
directive, TIC54X: TIC54X-Directivesfile
directive: Filefile
directive, MSP 430: MSP430 Directivesfill
directive: Fillfloat
directive: Floatfloat
directive, i386: i386-Floatfloat
directive, M680x0: M68K-Floatfloat
directive, M68HC11: M68HC11-Floatfloat
directive, RX: RX-Floatfloat
directive, TIC54X: TIC54X-Directivesfloat
directive, VAX: VAX-floatfloat
directive, x86-64: i386-Float\f
): Stringsfunc
directive: Funcgfloat
directive, VAX: VAX-directivesglobal
: Z8000 Directivesglobal
directive: Globalglobal
directive, TIC54X: TIC54X-Directivesgp
register, MIPS: MIPS Small Datagp
register, V850: V850-Regshalf
directive, SPARC: Sparc-Directiveshalf
directive, TIC54X: TIC54X-Directives\
xd...): Stringshfloat
directive, VAX: VAX-directiveshi
pseudo-op, V850: V850 Opcodeshi0
pseudo-op, V850: V850 Opcodeshidden
directive: Hiddenhigh
directive, M32R: M32R-Directiveshilo
pseudo-op, V850: V850 Opcodeshword
directive: hwordmul
, imul
instructions: i386-Notesident
directive: Identif
directive: Ififb
directive: Ififc
directive: Ififdef
directive: Ififeq
directive: Ififeqs
directive: Ififge
directive: Ififgt
directive: Ififle
directive: Ififlt
directive: Ififnb
directive: Ififnc
directive: Ififndef
directive: Ififne
directive: Ififnes
directive: Ififnotdef
directive: Ifimul
instruction, i386: i386-Notesimul
instruction, x86-64: i386-Notesincbin
directive: Incbininclude
directive: Includeinclude
directive search path: Iint
directive: Intint
directive, H8/300: H8/300 Directivesint
directive, i386: i386-Floatint
directive, TIC54X: TIC54X-Directivesint
directive, x86-64: i386-Floatinternal
directive: Internalirp
directive: Irpirpc
directive: IrpcL16SI
instructions, relaxation: Xtensa Immediate RelaxationL16UI
instructions, relaxation: Xtensa Immediate RelaxationL32I
instructions, relaxation: Xtensa Immediate RelaxationL8UI
instructions, relaxation: Xtensa Immediate Relaxation:
): Statementslabel
directive, TIC54X: TIC54X-Directiveslargecomm
directive, ELF: i386-Directiveslcomm
directive: ARC Directiveslcomm
directive: Lcommlcomm
directive, COFF: i386-Directiveslcommon
directive, ARC: ARC Directivesld
: Objectldouble
directive M680x0: M68K-Floatldouble
directive M68HC11: M68HC11-Floatldouble
directive, TIC54X: TIC54X-DirectivesLDR reg,=<label>
pseudo op, ARM: ARM Opcodeslength
directive, TIC54X: TIC54X-Directiveslflags
directive (ignored): Lflagsline
directive: Lineline
directive, MSP 430: MSP430 Directives#
: Commentslinkonce
directive: Linkoncelist
directive: Listlist
directive, TIC54X: TIC54X-Directivesliteral
directive: Literal Directiveliteral_position
directive: Literal Position Directiveliteral_prefix
directive: Literal Prefix Directiveln
directive: Lnlo
pseudo-op, V850: V850 Opcodesloc
directive: Locloc_mark_labels
directive: Loc_mark_labelslocal
directive: Locallong
directive: Longlong
directive, i386: i386-Floatlong
directive, TIC54X: TIC54X-Directiveslong
directive, x86-64: i386-Floatlongcall
pseudo-op, V850: V850 Opcodeslongcalls
directive: Longcalls Directivelongjump
pseudo-op, V850: V850 Opcodesloop
directive, TIC54X: TIC54X-DirectivesLOOP
instructions, alignment: Xtensa Automatic Alignmentlow
directive, M32R: M32R-Directiveslp
register, V850: V850-Regslval
: Z8000 DirectivesmA6
command-line option, ARC: ARC OptionsmA7
command-line option, ARC: ARC Optionsmacro
directive: Macromacro
directive, TIC54X: TIC54X-Directivesmarc600
command-line option, ARC: ARC OptionsmARC601
command-line option, ARC: ARC OptionsmARC700
command-line option, ARC: ARC OptionsmEM
command-line option, ARC: ARC OptionsmHS
command-line option, ARC: ARC Optionsmlib
directive, TIC54X: TIC54X-Directivesmlist
directive, TIC54X: TIC54X-Directivesmmregs
directive, TIC54X: TIC54X-Directivesmmsg
directive, TIC54X: TIC54X-Directivesmnolist
directive, TIC54X: TIC54X-Directivesmnps400
command-line option, ARC: ARC OptionsMOVI
instructions, relaxation: Xtensa Immediate Relaxationmri
directive: MRImspabi_attribute
directive, MSP430: MSP430 Directivesmul
instruction, i386: i386-Notesmul
instruction, x86-64: i386-Notesname
: Z8000 Directivesnewblock
directive, TIC54X: TIC54X-Directives\n
): Stringsno-absolute-literals
directive: Absolute Literals Directiveno-longcalls
directive: Longcalls Directiveno-schedule
directive: Schedule Directiveno-transform
directive: Transform Directivenolist
directive: Nolistnolist
directive, TIC54X: TIC54X-DirectivesNOP
pseudo op, ARM: ARM Opcodesnops
directive: Nopsnword
directive, SPARC: Sparc-Directivesocta
directive: Octa\
ddd): Stringsoffset
directive: Offsetoffset
directive, V850: V850 Directivesoption
directive, TIC54X: TIC54X-Directivesorg
directive: Orga.out
symbol: Symbol Otherp2align
directive: P2alignp2alignl
directive: P2alignp2alignw
directive: P2align.include
: Ipopsection
directive: PopSectionprevious
directive: Previousprint
directive: Printproc
directive, SPARC: Sparc-Directivesprofiler
directive, MSP 430: MSP430 Directivesprotected
directive: Protectedpsize
directive: Psizepstring
directive, TIC54X: TIC54X-Directivespsw
register, V850: V850-Regspurgem
directive: Purgempushsection
directive: PushSectionquad
directive: Quadquad
directive, i386: i386-Floatquad
directive, x86-64: i386-Floatref
directive, TIC54X: TIC54X-Directivesrefsym
directive, MSP 430: MSP430 Directivesregister
directive, SPARC: Sparc-DirectivesADDI
instructions: Xtensa Immediate RelaxationL16SI
instructions: Xtensa Immediate RelaxationL16UI
instructions: Xtensa Immediate RelaxationL32I
instructions: Xtensa Immediate RelaxationL8UI
instructions: Xtensa Immediate RelaxationMOVI
instructions: Xtensa Immediate Relaxationreloc
directive: Relocrept
directive: Reptreserve
directive, SPARC: Sparc-Directivesrsect
: Z8000 Directivessblock
directive, TIC54X: TIC54X-Directivessbttl
directive: Sbttlschedule
directive: Schedule Directivescl
directive: Sclsdaoff
pseudo-op, V850: V850 Opcodes.include
: Isect
directive, TIC54X: TIC54X-Directivessection
directive (COFF version): Sectionsection
directive (ELF version): Sectionsection
directive, V850: V850 Directivesseg
directive, SPARC: Sparc-Directivessegm
: Z8000 Directivesset
directive: Setset
directive, TIC54X: TIC54X-Directivesshigh
directive, M32R: M32R-Directivesshort
directive: Shortshort
directive, TIC54X: TIC54X-Directivessingle
directive: Singlesingle
directive, i386: i386-Floatsingle
directive, x86-64: i386-Floatsize
directive (COFF version): Sizesize
directive (ELF version): Sizeskip
directive: Skipskip
directive, M680x0: M68K-Directivesskip
directive, SPARC: Sparc-Directivessleb128
directive: Sleb128sp
register, V850: V850-Regsspace
directive: Spacespace
directive, TIC54X: TIC54X-Directivessslist
directive, TIC54X: TIC54X-Directivesssnolist
directive, TIC54X: TIC54X-Directivesstabd
directive: Stabstabn
directive: Stabstabs
directive: Stabstab
x directives: Stabstring
directive: Stringstring
directive on HPPA: HPPA Directivesstring
directive, TIC54X: TIC54X-Directivesstring16
directive: Stringstring32
directive: Stringstring64
directive: Stringstring8
directive: Stringstruct
directive: Structstruct
directive, TIC54X: TIC54X-Directivessubsection
directive: SubSectionsval
: Z8000 Directivesa.out
: a.out Symbolssymver
directive: Symver\t
): Stringstab
directive, TIC54X: TIC54X-Directivestag
directive: Tagtag
directive, TIC54X: TIC54X-Directivestdaoff
pseudo-op, V850: V850 Opcodestext
directive: Texttfloat
directive, i386: i386-Floattfloat
directive, x86-64: i386-Floattitle
directive: Titletp
register, V850: V850-Regstransform
directive: Transform Directivetype
directive (COFF version): Typetype
directive (ELF version): Typeualong
directive, SH: SH Directivesuaquad
directive, SH: SH Directivesuaword
directive, SH: SH Directivesubyte
directive, TIC54X: TIC54X-Directivesuchar
directive, TIC54X: TIC54X-Directivesuhalf
directive, TIC54X: TIC54X-Directivesuint
directive, TIC54X: TIC54X-Directivesuleb128
directive: Uleb128ulong
directive, TIC54X: TIC54X-Directivesunion
directive, TIC54X: TIC54X-Directivesunsegm
: Z8000 Directivesusect
directive, TIC54X: TIC54X-Directivesushort
directive, TIC54X: TIC54X-Directivesuword
directive, TIC54X: TIC54X-Directivesval
directive: Valvalue
directive: i386-Directivesvar
directive, TIC54X: TIC54X-Directivesversion
directive: Versionversion
directive, TIC54X: TIC54X-Directivesvtable_entry
directive: VTableEntryvtable_inherit
directive: VTableInheritweak
directive: Weakweakref
directive: Weakrefwidth
directive, TIC54X: TIC54X-Directiveswmsg
directive, TIC54X: TIC54X-Directivesword
directive: Wordword
directive, H8/300: H8/300 Directivesword
directive, i386: i386-Floatword
directive, SPARC: Sparc-Directivesword
directive, TIC54X: TIC54X-Directivesword
directive, x86-64: i386-Floatwval
: Z8000 Directivesxfloat
directive, TIC54X: TIC54X-Directivesxlong
directive, TIC54X: TIC54X-Directivesxword
directive, SPARC: Sparc-Directiveszdaoff
pseudo-op, V850: V850 Opcodeszero
directive: Zerozero
register, V850: V850-Regs[1] This
is not the same as the executable image file alignment controlled by ld
's
‘--section-alignment’ option; image file sections in PE are aligned to
multiples of 4096, which is far too large an alignment for ordinary variables.
It is rather the default alignment for (non-debug) sections within object
(‘*.o’) files, which are less strictly aligned.
[2] The term “macro” is somewhat overloaded here, since
these macros have no relation to those defined by .macro
,
see .macro
.
[3] Literals for the
.init
and .fini
sections are always placed in separate
sections, even when ‘--text-section-literals’ is enabled.
[4] Any more details?